NXP Semiconductors
UM12018
FRDM-MCXN947 Board User Manual
On the FRDM-MCXN947 board, the USB1_DM and USB1_DP signals from the target MCU connect to the
onboard USB connector (J11) directly through a common mode choke. The common mode choke is included for
noise suppression on the DM / DP signals.
2.4 Ethernet interface
The target MCU (MCXN947) features one Ethernet controller (ENET0) module.
On the FRDM-MCXN947 board, the Ethernet controller connects to an RJ45 connector through an Ethernet
PHY transceiver. The transmit, receive, and other Ethernet signals are on the P1 port pins. The FRDM-
MCXN947 only supports RMII configuration. For this reason, the TXD3 and TXD2 pins of the Ethernet PHY
(LAN8741A-EN) have been grounded through resistors R68 and R67, respectively.
Table 12 describes the onboard devices supporting the Ethernet interface.
Part identifier Part name and Manufacturer Description
J16 Heling MJ88B-B011-RVL11-P Shielded RJ45 connector jack with magnetic built-in to connect to
an Ethernet cable
U9 Microchip Technology LAN8741
A-EN
Single-chip 10 /100 Mbit/s RMII Ethernet PHY compliant with
IEEE802.3/802.3u (Fast Ethernet), ISO 802-3/IEEE 802.3 (10
BASE-T), and Energy-Efficient Ethernet IEEE 802.3az
T1 BOURNS PT61018PEL Dual-channel 16-pin Ethernet transformer for LAN 10/100 Base-Tx
Table 12. Ethernet interface devices
Input to the XTAL1/CLKIN pin of the Ethernet PHY is a 50 MHz clock from an external 50 MHz crystal oscillator
(Y3). The oscillator is enabled by default. The clock circuit also provides a provision to feed the clock back into
the target MCU (MCXN947) through Port P1 pin 4 (P1_4/ENET_TXCLK).
Note: The 50 MHz oscillator can be disabled by populating the R154 resistor.
2.5 FlexCAN interface
The controller area network (FlexCAN) is a full implementation of the CAN protocol specification, the CAN
with flexible data rate (CAN FD) protocol, and the CAN 2.0 version B protocol, which supports both standard
and extended message frames and long payloads. The target MCU (MCXN947) supports two CAN (w/wo FD)
controllers (CAN0 to CAN1).
On FRDM-MCXN947, only the CAN0 controller is used. The CAN0 controller connects to a 4-pin CAN header
through a CAN transceiver (TJA1057GTK/3Z). The CAN0_TXD and CAN0_RXD signals are through ports
P1_10 and P1_11, respectively.
Table 13 describes the HS CAN transceiver and 4-pin CAN header used on the board.
Part identifier Manufacturing part
number
Description
U10 TJA1057GTK/3Z High-speed CAN transceiver. It provides an interface between the CAN0
controller and the physical two-wire CAN0 bus.
J10 - 4-pin CAN header. It is connected to the CAN0 bus and allows external
connection with the bus.
Table 13. High-speed CAN transceiver and header
Figure 10 shows the FlexCAN interface schematic.
UM12018 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.
User manual Rev. 1 — 20 January 2024
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