NXP Semiconductors UM10204 User Manual

UM10204
I
2
C-bus specification and user manual
Rev. 5 — 9 October 2012 User manual
Document information
Info Content
Keywords I2C, I2C-bus, Standard-mode, Fast-mode, Fast-mode Plus, Fm+,
Ultra Fast-mode, UFm, High Speed, Hs, inter-IC, SDA, SCL, USDA, USCL
Abstract Philips Semiconductors (now NXP Semiconductors) developed a simple
bidirectional 2-wire bus for efficient inter-IC control. This bus is called the
Inter-IC or I
2
C-bus. Only two bus lines are required: a serial data line
(SDA) and a serial clock line (SCL). Serial, 8-bit oriented, bidirectional
data transfers can be made at up to 100 kbit/s in the Standard-mode, up to
400 kbit/s in the Fast-mode, up to 1 Mbit/s in the Fast-mode Plus (Fm+), or
up to 3.4 Mbit/s in the High-speed mode. The Ultra Fast-mode is a
uni-directional mode with data transfers of up to 5 Mbit/s.

NXP Semiconductors UM10204 Specifications

General

Document Number	UM10204
Standard Mode Speed	100 kbit/s
Fast Mode Speed	400 kbit/s
Fast Mode Plus Speed	1 Mbit/s
High Speed Mode	3.4 Mbit/s
Ultra Fast Mode	5 Mbit/s
Bus Capacitance Limit	400 pF
Title	I2C-bus specification and user manual
Protocol	I2C
Voltage Levels	Typically 3.3V or 5V.
Addressing	7-bit or 10-bit addressing

Summary

Revision History

Modifications

Details of changes made in each revision of the I2C-bus specification.

1. Introduction

2. I2C-bus features

2.1 Designer benefits

Benefits of I2C-bus compatible ICs for system design and prototyping.

2.2 Manufacturer benefits

Advantages of I2C-bus compatible ICs for equipment manufacturers, reducing PCB complexity and cost.

2.3 IC designer benefits

Advantages of I2C-bus interface for microcontroller designers, conserving pins and simplifying design.

3. The I2C-bus protocol

3.1 Standard-mode, Fast-mode and Fast-mode Plus I2C-bus protocols

Detailed description of the Standard, Fast, and Fast-mode Plus I2C-bus protocols and their operation.

3.2 Ultra Fast-mode I2C-bus protocol

Description of the unidirectional Ultra Fast-mode I2C-bus protocol for high-speed data transfer.

4. Other uses of the I2C-bus communications protocol

4.1 CBUS compatibility

Connecting CBUS receivers to the Standard-mode I2C-bus with specific protocol requirements.

4.2 SMBus - System Management Bus

Using I2C hardware for SMBus systems, including address resolution and dynamic allocation.

4.3 PMBus - Power Management Bus

Communicating with power converters over SMBus for intelligent control and identical device function.

4.4 Intelligent Platform Management Interface (IPMI)

Standardized interface for intelligent platform management hardware, monitoring and diagnosis.

4.5 Advanced Telecom Computing Architecture (ATCA)

I2C-bus used for thermal management and communication between boards in telecom hardware.

4.6 Display Data Channel (DDC)

DDC for monitor-host communication, enabling monitor function control via I2C standard mode.

5. Bus speeds

5.1 Fast-mode

Details on Fast-mode I2C-bus operation up to 400 kbit/s, including protocol and timing adaptations.

5.2 Fast-mode Plus

Fast-mode Plus for speeds up to 1 Mbit/s with increased drive current and bus capacitance tolerance.

5.3 Hs-mode

High-speed mode for up to 3.4 Mbit/s, detailing transfer requirements and system configurations.

5.4 Ultra Fast-mode

Ultra Fast-mode for unidirectional transfers up to 5 Mbit/s, using push-pull drivers.

6. Electrical specifications and timing for I/O stages and bus lines

6.1 Standard-, Fast-, and Fast-mode Plus devices

I/O levels, current, spike suppression, output slope control, and timing for these modes.

6.2 Hs-mode devices

Timing parameters and bus line characteristics for Hs-mode devices, including rise/fall times.

6.3 Ultra Fast-mode devices

I/O levels, current, and timing specifications for Ultra Fast-mode devices, defining bit rates.

7. Electrical connections of I2C-bus devices to the bus lines

7.1 Pull-up resistor sizing

Calculating pull-up resistor values based on bus capacitance, voltage, and rise time requirements.

7.2 Operating above the maximum allowable bus capacitance

Strategies to handle bus capacitance limits, including reduced speed and buffers.

7.3 Series protection resistors

Using series resistors for protection against voltage spikes on SDA and SCL lines.

7.4 Input leakage

Understanding input leakage current and its impact on maximum pull-up resistor value.

7.5 Wiring pattern of the bus lines

Recommended wiring patterns for minimizing interference and crosstalk on bus lines.

8. Abbreviations

9. Legal information

9.1 Definitions

Definitions of key terms used throughout the I2C-bus specification document.

9.2 Disclaimers

Warranty, liability, suitability for use, and export control disclaimers for NXP products.

9.3 Trademarks

List of referenced trademarks, product names, and service names.