UM10204 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
User manual Rev. 5 — 9 October 2012 26 of 64
NXP Semiconductors
UM10204
I
2
C-bus specification and user manual
START and STOP conditions are always generated by the master. The bus is considered
to be busy after the START condition. The bus is considered to be free again a certain
time after the STOP condition. This bus free situation is specified in Section 6
. The bus
stays busy if a repeated START (Sr) is generated instead of a STOP condition. In this
respect, the START (S) and repeated START (Sr) conditions are functionally identical. For
the remainder of this document, therefore, the S symbol is used as a generic term to
represent both the START and repeated START conditions, unless Sr is particularly
relevant.
Detection of START and STOP conditions by devices connected to the bus is easy if they
incorporate the necessary interfacing hardware. However, microcontrollers with no such
interface have to sample the USDA line at least twice per clock period to sense the
transition.
3.2.5 Byte format
Every byte put on the USDA line must be eight bits long. The number of bytes that can be
transmitted per transfer is unrestricted. The master drives the USDA HIGH after each byte
during the Acknowledge cycle. Data is transferred with the Most Significant Bit (MSB) first
(see Figure 25
). A slave is not allowed to hold the clock LOW if it cannot receive another
complete byte of data or while it is performing some other function, for example servicing
an internal interrupt.
Fig 24. Definition of START and STOP conditions for UFm I
2
C-bus
002aaf145
USDA
USCL
P
STOP condition
S
START condition
Fig 25. Data transfer on the UFm I
2
C-bus
S or Sr Sr or P
USDA
USCL
MSB
12 89 12
3 to 7
8
NACK NACK
002aag657
START or
repeated START
condition
STOP or
repeated START
condition
byte complete,
interrupt within slave
P
Sr
Master drives the line HIGH on 9th clock cycle.
Slave never drives the USDA line.
9
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