UM10204 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
User manual Rev. 5 — 9 October 2012 57 of 64
NXP Semiconductors
UM10204
I
2
C-bus specification and user manual
capacitance. Keep in mind that adding a buffer always adds delays — a buffer delay plus
an additional transition time to each edge, which reduces the maximum operating
frequency and may also introduce special V
IL
and V
OL
considerations.
Refer to application notes AN255, I
2
C / SMBus Repeaters, Hubs and Expanders and
AN262, PCA954x Family of I
2
C / SMBus Multiplexers and Switches for more details on
this subject and the devices available from NXP Semiconductors.
7.2.4 Switched pull-up circuit
The supply voltage (V
DD
) and the maximum output LOW level determine the minimum
value of pull-up resistor R
p
(see Section 7.1). For example, with a supply voltage of
V
DD
=5V± 10 % and V
OL(max)
= 0.4 V at 3 mA, R
p(min)
=(5.5− 0.4) / 0.003 = 1.7 kΩ. As
shown in Figure 42
, this value of R
p
limits the maximum bus capacitance to about 200 pF
to meet the maximum t
r
requirement of 300 ns. If the bus has a higher capacitance than
this, a switched pull-up circuit (as shown in Figure 44
) can be used.
Remark: Some buffers allow V
DD1
and V
DD2
to be different levels.
Fig 43. Using a buffer to divide bus capacitance
To Next Page
Loading...
