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Omron SYSMAC C40K User Manual

Omron SYSMAC C40K
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107
SFT(10) shifts an execution condition into a shift register. SFT(10) is con-
trolled by three execution conditions, I, P, and R. If SFT(10) is executed and
1) execution condition P is ON and was OFF the last execution and 2) R is
OFF, then execution condition I is shifted into the rightmost bit of a shift regis-
ter defined between St and E, i.e., if I is ON, a 1 is shifted into the register; if I
is OFF, a 0 is shifted in. When I is shifted into the register, all bits previously
in the register are shifted to the left and the leftmost bit of the register is lost.
Execution
condition I
Lost
data
E
St + 1, St + 2, ...
St
The execution condition on P functions like a differentiated instruction, i.e., I
will be shifted into the register only when P is ON and was OFF the last time
SFT(10) was executed. If execution condition P has not changed or has gone
from ON to OFF, the shift register will remain unaffected.
St designates the rightmost word of the shift register; E designates the left-
most. The shift register includes both of these words and all words between
them. The same word may be designated for St and E to create a 16-bit (i.e.,
1-word) shift register.
When execution condition R goes ON, all bits in the shift register will be
turned OFF (i.e., set to 0) and the shift register will not operate until R goes
OFF again.
There are no flags affected by SFT(10).
The following example uses the 1-second clock pulse bit (1902) to so that the
execution condition produced by 0005 is shifted into a 3-word register be-
tween 10 and 12 every second.
I
P
SFT(10)
10
12
R
0005
1902
0006
Address Instruction Operands
0000 LD 0005
0001 LD 1902
0002 LD 0006
0003 SFT(10)
10
12
The following program is used to control the status of the 17th bit of a shift
register running from IR 00 through IR 01 (i.e. bit 00 of IR 01). When the 17th
bit is to be set, 0204 is turned ON. This causes the jump for JMP(04) 00 not
to be made for that one cycle and IR 0100 (the 17th bit) will be turned ON.
Description
Flags
Example 1:
Basic Application
Example 2:
Controlling Bits in Shift
Registers
Data Shifting Section 5-12

Table of Contents

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Questions and Answers:

Omron SYSMAC C40K Specifications

General IconGeneral
BrandOmron
ModelSYSMAC C40K
CategoryController
LanguageEnglish

Summary

About this Manual

PRECAUTIONS

Intended Audience

Specifies the target personnel for the manual, requiring knowledge of electrical systems.

General Precautions

Details user responsibilities for product operation and consulting OMRON for specific applications.

Safety Precautions

Highlights critical warnings about electric shock and unit modification while power is supplied.

Operating Environment Precautions

Lists locations to avoid for control system operation due to environmental factors.

Application Precautions

Provides crucial safety guidelines for grounding, power supply, and system wiring.

SECTION 1 Background

1-1 Introduction

Introduces Programmable Controllers (PCs) and the manual's scope on ladder-diagram programming.

1-2 Relay Circuits: The Roots of PC Logic

Explains the historical origin of PCs from relay control systems and programming terminology.

1-3 PC Terminology

Defines key terms like PC, input/output devices, and control systems for clarity.

1-5 Overview of PC Operation

Outlines the basic steps for programming and operating a K-type PC system.

1-6 Peripheral Devices

Details peripheral devices used for programming, monitoring, and interfacing PCs.

SECTION 2 Hardware Considerations

2-1 Introduction

Provides information on hardware aspects relevant to programming and software operation.

2-2 Indicators

Explains CPU indicators (POWER, RUN, ERR, ALARM) for visual feedback on PC operation.

2-3 PC Configuration

Describes the components of a K-type PC system, including CPU and optional units.

SECTION 3 Memory Areas

3-1 Introduction

Explains the purpose of various memory areas for data management and control.

3-2 Data Area Structure

Details the structure, acronyms, ranges, and functions of PC memory areas.

3-3 Internal Relay (IR) Area

Describes the IR area for I/O points, work bits, and their access methods.

3-4 Special Relay (SR) Area

Covers SR area flags and control bits for system monitoring, clock pulses, and error signaling.

3-5 Data Memory (DM) Area

Explains the DM area for internal data storage and manipulation, accessible only by word.

3-6 Holding Relay (HR) Area

Details the HR area for data storage and manipulation that retains status during power interruptions.

3-7 Timer/Counter (TC) Area

Covers the TC area for programming timers and counters, including completion flags and set values.

3-8 Temporary Relay (TR) Area

Explains the TR area bits used for enabling branching in ladder diagrams.

SECTION 4 Writing and Inputting the Program

4-1 Introduction

Explains converting ladder diagrams to mnemonic code and basic programming steps.

4-3 The Ladder Diagram

Describes the structure and components of a ladder diagram, including conditions and instructions.

4-4 The Programming Console

Details the keyboard layout and PC modes (RUN, MONITOR, PROGRAM) of the programming console.

4-5 Preparation for Operation

Covers essential procedures before initial program input, including password entry and memory clearing.

4-6 Inputting, Modifying, and Checking the Program

Explains procedures for entering, modifying, checking programs, and displaying cycle time.

4-7 Controlling Bit Status

Describes instructions like OUT, DIFU, DIFD, and KEEP for controlling individual bit status.

4-9 Programming Precautions

Provides guidelines on drawing clear diagrams, using TR bits, and avoiding complex structures.

SECTION 5 Instruction Set

5-1 Introduction

Introduces the K-type PC instruction sets for programming control processes.

5-3 Instruction Format

Explains the structure of instructions, including operands, definers, and word usage.

5-5 Ladder Diagram Instructions

Details basic ladder instructions like LOAD, AND, OR, and logic block instructions.

5-6 Bit Control Instructions

Covers instructions for controlling individual bit status like OUT, DIFU, DIFD, and KEEP.

5-11 Timer and Counter Instructions

Explains timer and counter instructions, including TIM, CNT, TIMH, CNTR, HDM, and RDM.

5-12 Data Shifting

Describes instructions for creating and manipulating shift registers like SFT, SFTR, and WSFT.

5-13 Data Movement

Explains instructions for moving data between different memory addresses, including MOV and MVN.

5-14 DATA COMPARE – CMP(20)

Details the CMP instruction for comparing data and outputting results to flags.

5-15 Data Conversion

Covers instructions for converting data between formats like BCD and binary.

5-16 BCD Calculations

Explains BCD arithmetic instructions like ADD, SUB, MUL, and DIV.

5-18 Step Instructions

Describes STEP and SNXT instructions for setting up breakpoints and controlling program sections.

SECTION 6 Program Execution Timing

6-1 Introduction

Introduces program timing factors: cycle time and I/O response time.

6-2 Cycle Time

Explains CPU operation flow and factors affecting cycle time.

6-3 Calculating Cycle Time

Provides examples of calculating cycle time for single PCs and systems with additional units.

6-4 Instruction Execution Times

Lists execution times for K-type instructions, including conditions affecting them.

6-5 I/O Response Time

Explains the time taken for PC output signals after receiving input signals.

SECTION 7 Program Debugging and Execution

7-1 Introduction

Introduces procedures for inputting, debugging, monitoring, and controlling PCs.

7-2 Debugging

Covers eliminating execution errors, isolating programs, and displaying/clearing error messages.

7-3 Monitoring Operation and Modifying Data

Details operations for monitoring data and modifying PV/SV values for timers/counters.

7-4 Program Backup and Restore Operations

Explains procedures for backing up and restoring Program Memory using a cassette tape.

SECTION 8 Troubleshooting

8-1 Introduction

Introduces PC self-diagnostic functions for identifying and correcting system abnormalities.

8-2 Reading and Clearing Errors and Messages

Describes how to display and clear system error messages using the Programming Console.

8-3 Error Messages

Categorizes errors into non-fatal and fatal types and provides probable causes and corrections.

8-4 Error Flags

Lists SR area flags used for troubleshooting, like Battery Alarm and Cycle Time Error Flags.

Appendix A Standard Models

CPUs

Lists available K-type C-series CPUs with power supply, inputs, outputs, and model numbers.

I/O Units

Details various types of I/O Units, including specifications and model numbers.

Special Units

Describes Analog Timer Units, I/O Link Units, and related accessories.

Mounting Rail and Accessories

Lists mounting rails, end plates, and spacers for system installation.

Factory Intelligent Terminal (FIT)

Details the FIT computer, software, and included accessories.

Graphic Programming Console (GPC)

Lists GPC models, carrying cases, memory cassettes, and interface units.

Peripheral Devices

Lists peripheral devices like programming consoles, PROM writers, and interface units.

Appendix B Programming Instructions and Execution Times

Ladder Diagram Instructions

Details basic ladder instructions like LOAD, AND, OR, and logic block instructions.

Special Instructions

Describes instructions for I/O refresh, end wait, notation insert, and subroutines.

Instruction Execution Times

Lists execution times for all available K-types instructions.

Appendix C Programming Console Operations

Programming Operations

Details console operations for address designation, program search, and instruction manipulation.

Debugging Operations

Covers console operations for reading error messages and checking programs.

Monitoring and Data Changing Operations

Explains console operations for bit/word monitoring, forced set/reset, and data modification.

Cassette Tape Operations

Details procedures for saving, restoring, and comparing program memory data via cassette tape.

Appendix D Error and Arithmetic Flag Operation

Appendix E Binary–Hexadecimal–Decimal Table

Appendix F Word Assignment Recording Sheets

I/O Bits

Provides a template for recording I/O bit allocations and field device assignments.

Work Bits

Offers a template for recording work bit usage, area, word, and notes.

Data Storage

Provides a template for recording data storage, including word, contents, and notes.

Timers and Counters

Offers a template for recording timer/counter addresses, set values, and notes.

Appendix G Program Coding Sheet

Glossary

Revision History

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