215
Index
Numbers
16–TO–4 ENCODER – DMPX(77). See instruction set
4–TO–16 DECODER – MLPX(76). See instruction set
A
ADD(30). See instruction set
Always ON/OFF flags. See data areas
Analog Timer Unit. See instruction set
AND. See instruction set
AND LD. See instruction set
AND LOAD. See instruction set
AND NOT. See instruction set
AND NOT – AND NOT. See instruction set
arithmetic operation flags. See data areas
B
backup. See cassette tape operation
Battery Alarm Flag. See data areas
BCD ADD – ADD(30). See instruction set
BCD DIVIDE – DIV(33). See instruction set
BCD MULTIPLY – MUL(32). See instruction set
BCD SUBTRACT – SUB(31). See instruction set
BCD(24). See instruction set
BCD–TO–BINARY CONVERSION – BIN(23). See instruc-
tion set
BIN(23). See instruction set
binary table,
BINARY–TO–BCD CONVERSION – BCD(24). See instruc-
tion set
bits
force set/reset,
monitor,
self maintaining,
branching. See ladder diagram
C
Carry Flag. See data areas
cassette tape operation,
comparing program memory data,
error messages,
restoring program memory data,
saving program memory data,
CLC(41). See instruction set
CLEAR CARRY – CLC(41). See instruction set
Clock Pulse Bits. See data areas
CMP(20). See instruction set
CNTR(12). See instruction set
COMPARE – CMP(20). See instruction set
comparing program/memory data. See cassette tape operation
control bits, usage,
control system, definition of,
Counter – CNT. See instruction set
CPU indicators,
cycle time
calculating,
components,
displaying,
for instruction execution, ,
long duration,
Cycle Time Error Flag. See data areas
D
data areas
components,
Data Memory area,
HR,
IR
I/O bits available
in CPUs,
in Expansion I/O Units,
word allocation,
SR
Always OFF/ON Flags,
arithmetic flags, ,
Battery Alarm Flag,
Clock Pulse Bits,
Cycle Time Error Flag,
Error Flag, ,
First Cycle Flag,
high speed drum/counter reset,
Step Flag,
usage,
structure,
TC,
TR,
digit, monitor,
DIV(33). See instruction set
DM area. See data areas
DMPX(77). See instruction set
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