4
5
Program
Capacity
Two Series of Expansion Racks Up to 50 m Long for
Long-distance Expansion with Up to 72 Units and 7 Racks
Control Up to 960 Points with
Units Mounted to the CPU Rack
Large Capacity CPU Units for
Greater Component Control
Power
Improved Refresh Performance for Data Links,
Remote I/O Communications, and Protocol Macros
Wide Lineup Makes It Easy to
Build the Optimum System
250 Ksteps
120 Ksteps
60 Ksteps
30 Ksteps
20 Ksteps
10 Ksteps
Use the improved SYSMAC CS1 PLCs to scal e advanced systems to
the optimum size.
The evolution of
the SYSMAC CS1 is
accelerating advances in
the production site.
0.5 ms
0.3 ms
50 m
50 m
CPU
960 pts 1,280 pts 5,120 pts
Faster Instruction Execution and Faster Overall Performance
System Bus Baud Rate Doubled
Reduced Variation in Cycle Time During Data Processing
In addition to further improvements to
the instruction execution engine, which
is the core of overall PLC performance,
the high-speed RISC chip has been
upgraded to realize the fastest
instruction execution performance in
the industry. Also, the new models
have a mode where instruction
execution and peripheral processing are
processed in parallel, enabling balanced
improvements in overall speed.
Common Processing: 1.6 Times Faster
Previous CS1
models
New CS1
models
The figures above are for high-speed, general-purpose PLCs with
interchangeable boards.
40 ns
20 ns
170 ns
20 ns
37
µ
s
2.1
µ
s
5
16
Previous CS1
models
New CS1
models
Long
Number of I/O points
Product lineup (Example: LD instruction processing speed, DM capacity)
(LD: 0.02 µs, DM: 448 Kwords)
(LD: 0.02 µs, DM: 256 Kwords)
(LD: 0.04 µs, DM: 128 Kwords)
(LD: 0.02 µs, DM: 128 Kwords)
(LD: 0.02 µs, DM: 64 Kwords)
(LD: 0.02 µs, DM: 64 Kwords)
(LD: 0.04 µs, DM: 64 Kwords)
(LD: 0.04 µs, DM: 64 Kwords)
(LD: 0.04 µs, DM: 64 Kwords)
I/O Control Unit
2 Series of
Expansion Racks;
Up to 7 Racks Total
9 Units
Terminating
Resistor
I/O Interface Unit
Ten I/O Units of 96 points each
Five Analog Output
Units of 8 points each
Five Analog Input Units of
8 points each
Table data/
text string
processing
Table data/
text string
processing
Long
execution
time
The cycle is temporarily
extended when the instruction
is executed.
Variation
Only start of
processing
designated.
Background processing performed over several
cycles to limit the impact on cycle time and thus
reduce variation in cycle time.
Baud rate
doubled
System bus
CS1 Basic I/O Units
CS1 Special I/O Units
CS1 CPU Bus Units
CPU Unit
CPU Unit
DLNK
n
Immediate
I/O refresh
CIO Area words
allocated to CPU
Bus Units
DM Area words
allocated for CPU
Bus Units
Specific Area for
CPU Bus Units
CPU Bus
Unit n
Data exchange
during communi-
cations cycle
Controller Link Unit
DeviceNet Unit
Serial Communications
Unit
Data links
Remote I/O
Protocol macros
Refresh functionUnit name
Socket service based
on manipulation of
specific bits.
Ethernet Unit
The data transfer rate between the CPU
Unit and certain Units has been
doubled to further improve total system
performance.
Instructions that require long execution
time, such as table data processing
instructions and text string processing
instructions, are processed over
multiple cycles to minimize variations in
cycle time and maintain stable I/O
response.
With an expansion capacity of up
to 80 Units and 7 Racks over a
distance of 12 meters, the CS1 can
meet large-scale control needs.
Alternatively, an I/O Control Unit
and I/O Interface Units can be used
to connect two series of CS1 Long-
distance Expansion Racks
extending up to 50 m each and
containing a total of up to 72 Units
and 7 Racks. CS1 Basic I/O Units,
CS1 Special I/O Units, and CS1
CPU Bus Units can be mounted
anywhere on the Racks and
programmed without being
concerned about special remote
programming requirements.
Note: C200H Units cannot be mounted on the Long-
distance Expansion Racks.
The CS1 provides a high level of space
efficiency. As many as 960 I/O points
can be controlled by simply mounting
ten Basic I/O Units, with 96 I/O points
each, to the CPU Rack. Alternatively, as
many as 80 analog I/O points can be
used by mounting five Analog Input
Units and five Analog Output Units.
The CS1 CPU Units boast amazing
capacity with up to 5,120 I/O points, 250
Ksteps of programming, 448 Kwords of
data memory (including expanded data
memory) and 4,096 timers/counters
each. With a large programming
capacity, CS1 PLCs are not only ideal
for large-scale systems but easily
handle value-added applications and
other advanced data processing.
In the past, I/O refresh processing with
the CPU Bus Unit only occurred during
I/O refresh after instructions were
executed. With the new CS1, however,
I/O can be refreshed immediately by
using the DLNK instruction. Immediate
refreshing for processes peculiar to the
CPU Bus Unit, such as for data links and
DeviceNet remote I/O communications,
and for allocated CIO Area/DM Area
words when instructions are executed,
means greater refresh responsiveness
for CPU Bus Units.
A total of nine CPU Unit models
provide for a wide range of applications,
from small-scale systems to large. The
lineup also includes Memory Cards,
Serial Communications Boards, and a
wide selection of Special I/O Units that
can be used with any CPU Units to
flexibly build the system that meets the
requirements.
LD Instruction Processing Speed:
2 Times Faster
OUT Instruction Processing Speed:
8 Times Faster
Subroutine Processing Speed:
17.6 Times Faster
PCMIX Value: 3 Times Higher
The PCMIX is the average number of instructions that can be
executed in 1 µs and expresses the over execution performance of
the ladder program. This unit was conceived to allow comparing
the performance of PLCs from different manufacturers using a
common metric.
8 Ksteps/ms
Basic instructions only: 38 Ksteps/ms
Including special instructions:
22 Ksteps/ms
Previous CS1
models
New CS1
models
Cycle Time: 2.5 to 4.8 Times Shorter
(Cycle time for 128 inputs and 128 outputs)
With normal I/O refresh, 1-ms pulses are not lost even for large-
capacity (e.g., 30-Kstep) programs. This allows use in applications
requiring a high working accuracy, such as molding equipment.
The development of a special LSI to execute instructions and use
of a high-speed RISC chip enable high-speed processing at the
CPU.
Cycle time overhead due to program structuring is minimized.
Programs consisting mainly of basic instructions are processed at
ultrahigh speed.
Previous CS1
models
New CS1
models
Previous CS1
models
New CS1
models
Previous CS1
models
New CS1
models
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