62 - - - -
63 /NMI - - 3.3
64 /INT0 - - 3.3
65 /INT1 - - 3.3
66 BLKCK Subcode block clock pulse input I 0
67 /INT3 - - 3.3
68 DVDD4 CORE CPU system (1.6V) power supply - 1.6
69 SW1 Mechanics deck SW1 input I 0
70 CVSS7 GND - 0
71 MCLK Clock output (To Servo DSP) O 3.3
72 DVSS4 GND - 0
73 MLD Command load signal output (To Servo DSP) I 3.3
74 MDATA Command data output (To Servo DSP) O 3.3
75 DVDD4 I/O system (3.3V) power supply - 3.3
76 DVSS5 GND - 0
77 - Clock mode setting (L fixation) I 0
78 - Clock mode setting (H fixation) I 3.3
79 - Clock mode setting (L fixation) I -
80 - - - -
81 SW2 Mechanics deck SW2 input I 0
82 - - - -
83 EMU0 - - 0
84 EMU/OFF - - 3.3
85 TDO - - 3.3
86 TDI - - 0
87 /TRST - - 3.3
88 TCK - - 0
89 TMS - - 3.3
90 CVSS8 GND - 3.3
91 CVDD5 CORE CPU system (1.6V) power supply - 0
92 (GND) GND I 1.6
93 DVSS6 GND - 0
94 - - - -
95 CLKENA Oscillation output Cainabl signal O 3.3
http://tsn.pasc.panasonic.com/viewing/NAOT/CQ-C1300U/SVC/s0903000000.html (3 of 5)12.08.2005 4:04:07
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