FZ-10
Continued /IC600)
Continued (IC660)
Pin
No.
1/0
Pin
Name
Comment
Pin
No.
1/0
Pin Name Comment
86
Out
RCS
RAM
Chio selection
44 Out
P33
Traverse motor control
87 Out
RWE-
RAM
Data Write enable siqnal
45
Out
P32
Reset to IC700
88
Out
ROE-
RAM
Data
Read
enable
sicmal
46
Out
P31
Reset to stop the operation of the
89
VDD
Power suoolv
circuit where
MASH
circuit after.
90
vss
Ground
47
Out
P30
Command load
91
Out
RAO
Data buffer address 0
48
Out
P02
Command clock
92
Out
RA1
Data buffer address 1
49
lnout
P01
Sense inout
93
Out
RA2
Data buffer address 2
50
Out
P00
Command data
94
Out
RA3
Data buffer address 3
51
NC
No
connection
95
Out
RA4
Data buffer address 4
52
P97
No
connection
96
Out
RAS
Data buffer address 5
53
P96
No
connection
97
Out
RA6
Data buffer address 6
54
P95
No
connection
98
Out
RA7
Data buffer address 7
55
Out
P94
Access
LED
control
99
vss
Ground
56
P93
No
connection
100
Out
RAS
Data
buffer address 8
57
P92
No
connection
58
Out
P91
Clock for Q code
IC660
59
Out
P90
Play control
1
hi
M'
·C
IP
1croorocessor
:
(P/N MN1882410FZA)
60
AVSS
Analoq qround
Pin
No.
110
Pin
Name
Comment
61
SH
No
connection
1 Out
CA13
ROM
Address
13
62
VREF-
Reference voltaae
for
ADC
2 Out
CA12
ROM
Address 12
63
lnout
AD7
AD
converter inout 7
3 Out
CA11
ROM
Address
11
64
lnout
AD6
AD
converter inout 6
4 Out
CA10
ROM
Address
10
65
Input
ADS
AD
converter input 5
5 Out
CA9
ROM
Address 9
66
Input
AD4
AD
converter input 4
6 Out
CA8
ROM
Address 8
67
lnout AD3
AD
converter inout 3
7
Out
CA7
ROM
Address 7
68
Input
AD2
AD
converter input 2
8
Out
CA6
ROM
Address 6
69
Input
AD1
AD
converter input 1
9 Out
CAS
ROM
Address 5
70
lnout
ADO
AD
converter inout 0
10
Out
CA4
ROM
Address 4
71
VREF+
Reference
voltaQe
for
ADC
11
Out
CA3
ROM
Address 3
72 AVDD
Analoa oower supply
12
Out
CA2
ROM
Address 2
73
VDD
Power suoolv
13
Out
CA1
ROM
Address 1
74
D7
External data bus 7
14
Out
CAO
ROM
Address 0
75
D6
External data bus 6
15
Input
EX/
External
bus
selection
76
D5
External data bus 5
16
lnout
RST-
Reset
77
D4
External data bus 4
17
Out
RE-
Read
enable
78
D3
External data bus 3
18
Out
WE-
Write enable
79
D2
External data bus 2
19
TERM-
No
connection
80
D1
External data bus 1
20
R/W-
No
connection .
81
DO
External data bus 0
21
S3-
No
connection
82
vss
Ground
22
Out
S2-
liminq
siqnal qeneration
83
A15
External address
bus
15
23
Out
S1-
limina
sianal aeneration
84
A14 External address
bus
14
24
Out
SO-
ROM
chio selection
25
/nout
P26
DIR
/IC640 PIN-32)
IC700
26
lnout
P25
Sub-code block clock
DiQital
Servo
Processor (P/N MN662720RB)
27
Input
P24
Interrupt request from
IC640
Pin
No.
1/0
Pin
Name
Comment
28
lnout
P22
liminq
sianal
1 Out BCLK Bit clock output for SDATA
29
Out
P21
Traverse Unit control
2 Out LRCK UR selection
30
lnout
P20
Comolement flaa
3 Out
SRDATA Serial data
31
Out
OSC2
Oscillator cutout
4 lnout
DVDD1
Diqital power supply
32
lnout
OSC1
Oscillator input
5 Input
DVSS1
Diaital around
33
vss
Ground
6 Out
TX
Diaital audio interface
34 Input
X1
Oscillator inout /Low speed)
7 lnout MCLK Command clock
35 Out
XO
Oscillator output (Low soeedl
8 lnout
MDATA Command data
36
lnout
P17
Door ooen/close
9 Input
MLD
Command load
37
Input
P16
Reset
of pick-uo location
10
Out SENSE Sense cutout
38
P15
No
connection
11
Out FLOCK- Focus servo control
39
Input
P14
DSP
status sianal
12
Out TLOCK- Trackinq servo control
40
Input
P13
Q code inout
13
Out
BLKCK
Sub
code block clock
41
Input
P12
Trackinq servo control
14
Input
SOCK Clock for Q reaister
42
lnout
P11
Focus servo control
15
Out SUBQ
Q code cutout
43
Out
P10
S.Motor control
16
lnout DMUTE Mutina
2-12
To Next Page
Loading...
