Philips 32HF7445/93 - Page 71

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Circuit Descriptions, Abbreviation List, and IC Data Sheets
EN 71TPT1.1HA LA 9.
9.4.5 Diagram B5A, SVP_PX66LX66
Figure 9-7 Internal block diagram and pin configuration
Block Diagram
Pin Configuration
H_17360_057.eps
140907
SVP™PX66
Single 8bit/10bit LVDS
Channel (1366x768P
Output)
ADC
108
Mhz
3D Video
Decoder
DDR/SDR
108Mhz
Din_portA
(32 bit) Input
Single Channel
10-bit LVDS Tx
(85Mhz per
channel)
Analog Mux
(24 + 8) bit in
2 x PWM
3 CVBS
2 Chroma
PC RGB x 1
(up to SXGA 60Hz)
Ypbpr x 2 (D1/D2/D3/D4)
2FB & 2 FS (SCART)
ASS/DSS
UMAC
Memory Control
ICSC
Color
Management
MP
3D motion
Deinterlacer
PIP
Deinterlacer
MP
6
Generation
Scaler
PIP
Scaler
MP
Noise
Reduction
MP
Sharpness
Control
CRTC
10bit Gama
LCD Over
Drive
CSC
White
Balance
MCU
Interface
GPIO I2C PWM
VBI
Slicer
OSD
Engine
I2C
GPIO
CVBS_OUT
Panel
Timing
PCLK/H/V
CVBS Out x 2/
Svideo_out
HDMI/HDCP
RX
HDMI/DVI Signals In
I2S &
SPDIF
I2S & SPDIF
MP
Dynamic
Contrast
32 bit DDR
CPU
8/16 bit
CPU bus
Flash
ROM
108Mhz Din_portB
(16 bit) Input/Output
(8/16) bit in or (8 bit in, 8bit out)
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A
MD27 MD26 MD25 MD23 MD21 DQM2 MD19 MD12 DQM1 MD7 MD6 DQM0 MD2 TA1P TB1P TC1P TCLK1P TD1P TE1P Revd
A
B
DQM3 DQS3 VSS VDDM MD22 DQS2 MD18 MD13 DQS1 MD8 MD5
DQS0
MD1
TA1M TB1M
TC1M
TCLK1M
TD1M TE1M
Revd B
C MD28 MD29 MD30 VDDM
MD24 VSS
MD17
MD14
VSS
MD9
MD4
VSS
MD0
VDDC VDDC
LVDS_V
SSD
LVDS_VD
DO
LVDS_VSS
O
LVDS_VSS
O
Revd
C
DMCK0 VSS MD31 VDDM
VDDM MD20 MD16 MD15 MD11
MD10
VDDM
MD3
VDDC
VDDC VDDC
LVDS_V
DDD
LVDS_VD
DO
LVDS_VD
DP
Rsvd
Rsvd D
E
MCK0# VDDR MVREF
VSSR VDDM
VDDM VSSR
VDDR
VDDM VDDM VDDM
VDDM VDDC
VDDC
VDDC
LVDS_V
SSA
LVDS_VD
DA
LVDS_VSS
P
Rsvd Rsvd E
F
MA11 MA10 MA9
MA8 VDDM
V5SF
TESTMOD
E
RESET Rsvd Rsvd
F
G
MA4 MA5 MA6 MA7
VDDM
VDDC PWM0 INTN Rsvd Rsvd
G
H
MA3 MA2 MA1 MA0
VDDC
dvsRdvsRLCSADSCDDVSSVSSVSSVSSVSSVSSV
H
J
#DR#RWELASC_UPCCDDVSSVSSVSSVSSVSSVSSVCDDV#0SC#1SC#SAR#SAC
J
K
WE# CLKE BA0 BA1
VDDC
VSS VSS VSS VSS VSS VSS
VDDC
AD4AD5AD6AD7
K
L
RXC+ RXC-
TMDS_G
ND
PVCC
VSS
3DA2DA1DA0DAHDDVSSVSSVSSVSSVSSVSSV
L
M
RX0+ RX0-
TMDS_G
ND
AVCC
ANTSTO
VSS VSS VSS VSS VSS VSS
VDDH ADDR7 ADDR6 ADDR5 ADDR4 M
N
RX1+ RX1-
TMDS_G
ND
AVCC
AVCC
VSS VSS VSS VSS VSS VSS
VDDH ADDR0 ADDR1 ADDR2 ADDR3 N
P
RX2+ RX2-
TMDS_G
ND
AVCC
DGND VDDH VS VSS HS Rsvd P
R
TMDS_G
ND
AVDDLL
PLL
PAVSS2 PLF2
REGVC
C
VDDC Rsvd Rsvd DPB_9 DPB_8 R
T
AVSSLLP
LL
PAVSS1 PAVDD1 PAVDD2
AVSS_A
DC1
AVSS_AD
C4
AVSS_AD
C2
AVDD_AD
C3
AVSS_AD
C3
PWR5V DSCL
VDDH VDDH VDDC VDDC VSS DPB_10 DPB_11 DPB_CLK DPB_12 T
U
AVDDAP
LL
MLF1
AVDD3_
OUTBUF
FB2
AVDD_A
DC1
AVDD_AD
C4
AVDD_AD
C2
PC_R
AVDD3_A
DC2
AIN_VS DSDA
WS DPA_22 DPA_15 DPA_14 DPA_8 DPA_7 DPB_15 DPB_14 DPB_13 U
V
AVSSAP
LL
CVBS_O
UT2
AVDD3_
BG_ASS
FS1
VREFN_
1
Y_G1 VREFN_2 PR_R3
C
AIN_HS SCDT
SD0 DPA_21 DPA_16 DPA_13 DPA_9 DPA_6 DPA_1 DPB_HS DPB_VS V
W
XTALI
CVBS_O
UT1
AVSS_B
G_ASS
FS2
VREFP_
1
Y_G2 VREFP_2 PR_R2
PB_B1
PC_B
AUDIOCL
K
SPDIF DPA_20 DPA_17 DPA_12 DPA_10 DPA_5 DPA_2 DPA_0 DPB_DE W
Y
XTALO AVSS_O
UTBUF
AVDD3_
ADC1
CVBS1
FB1
Y_G3 PC_G PR_R1
PB_B2
PB_B3 SCK DPA_23 DPA_19 DPA_18 DPA_CLK DPA_11 DPA_4 DPA_3 DPA_HS
DPA_VS Y
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