Philips 32PFS5709/12 - Page 81

IC Data Sheets
EN 81TPM14.2E LA 8.
2014-Sep-26
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8.7 Diagram 10-16-12 HDMI /Connector B12, SII9679CNUC (IC U713)
Figure 8-9 Internal block diagram and pin configuration
19616_301.eps
Block diagram
Pinning information
1VDD33OUT
2VDD5V IN
3RPWR5V
4CBUS HPD
5CoC GND
6AVDD10 DoC
7RXCN
8RXCP
9AVDD10
10VDD33
11RX0N
12RX0P
13RX1N
14RX1P
15RX2N
16RX2P
17AVDD10
18FVDD10
19VDDIO33
20
INT
21 22 23 24
GPIO0_CI2CA
G
PIO
1
_PSC
T
L
GPIO2
VDD10
28272625
TMODE
NC
NC NC
373635343332313029
NC
GPIO3
GPIO4
GPIO5
VDDIO33
RESET
N
VDD10
AVDD10_PLL
NC
38
TX_HPD
39 AVDD10 DP
40 TXCN
54
53
52
51
50
49
48
47
46
45
44
43
42
41
HSIC STB
XTAL VDD33
TX2P
XTAL OUT
XTAL IN
HSIC DAT
NC
TX1P
TX1N
TX0N
TX0P
TX2N
XTAL GND
TXCP
55 HSIC GND
56 VDD12OUT
57
HSIC VDD33
58
HSIC_VDD10
VDD10
59
SPI_MOSI
SPI_CS1
SPI_CS0
SPI_CLK
60616263
DSCL
LPSBV5V
WAKEUP
NC
MHL_CD
VDD10
CSCL
TDSDA
T
DSCL
VDDIO33
SPI_MISO
DSD
A
64656667686970717273747576
Top View
Si
I
9679
ePad (GND)
CSDA
SiI9679
Registers,
Configuration,
and Interrupt
Control Registers
Local I
2
C
RXCP/N
GPIO0_CI2CA
CBUS_HPD
MHL_CD
GPIO1_PSCTL
INT
VDD5V_IN
VCC33OUT
HSIC_DAT
HSIC_STB
RX0P/N
RX1P/N
RX2P/N
DDC_Rx
RPWR5V
RESETN
Video Data
Conversion
Logic
3V3
Regulator
HDMI/
MHL1, 2, 3
Receiver
1V8
Regulator
Rx HDCP
Authentication
Logic
Local I
2
C
Slave Logic
CBUS
Control
Rx DDC
Interface
Data
Tunneling
Tx DDC
Interface
SPI_MISO
SPI_MOSI
SPI_CS0
SPI_CLK
SPI Logic
HSIC PHY
DDC_Tx
GPIO2
SPI Slave
SPI Master
TX2P/N
TX1P/N
TX0P/N
TXCP/N
GPIO3
HDCP
Repeater
Logic
Tx HDCP
Encryption
Engine
HDCP
Decryption
Engine
Tx HDCP
Authentication
Logic
HDMI TMDS
Trans mitter
Audio
Output
Logic
Video Data
Audio Data
WS
SCK
MCLK
SD0_SPDIF
XTALIN
XTALOUT
OTP
(SiI9394
Dongle Only)
CEC_A
CEC
Interface
(SiI9394
Dongle Only)
Clock (CoC)
Data (DoC)
ISP
1V2 Regulator
SPI_CS1
TX_HPD
GPIO4
GPIO5
LPSB
LPSBV
WAKEUP
OSC
MCU