EN 186 3139 785 315329.
Circuit- and IC Description
PIN DESCRIPTION
Pin Name Input/Output Function
DGND G Digital Ground
AGND G Analog Ground
CLKIN_A I Pixel Clock Input for HD (74.25MHz Only , PS Only (27MHz), SD Only
(27MHz).
CLKIN_B I Pixel Clock Input. Requires a 27MHz reference clock for Progressive Scan
Mode or a 74.25MHz (74.1758MHz) reference clock in HDTV mode. This
Clock is only used in dual Modes.
COMP1,2 O Compensation Pin for DACs. Connect 0.1uF Capacitor from COMP pin to
V
AA
.
DAC A O CVBS/ GREEN/ Y / Y analog output.
DAC B O Chroma/ BLUE/ U / Pb analog output.
DAC C O Luma/ RED/ V / Pr analog output.
DAC D O In SD onlyu mode: CVBS/Green/Y analog outptu, in HD only mode and
simultaneous HD/SD mode: Y/Green [HD] analog output.
DAC E O In SD onlyu mode: Luma/Blue/U analog outptu, in HD only mode and
simultaneous HD/SD mode: Pr/Red analog output.
DAC F O In SD onlyu mode: Chroma/Red/ V analog outptu, in HD only mode and
simultaneous HD/SD mode: Pb/Blue [HD] analog output.
P_HSYNC
I Video Horizontal Sync Control Signal for HD in simultaneous Sd/HD
mode and HD mode only.
P_VSYNC
I Video Vertical Sync Control Signal for HD in simultaneous SD/HD mode and
HD mode only.
P_BLANK
I Video Blanking Control signal for HD in simultaneous SD/HD mode and HD
mode only.
S_BLANK
I Video Blanking Control Signal for SD only.
S_HSYNC
I Video Horizontal Sync Control Signal for SD only.
S_VSYNC
I Video Vertical Sync Control Signal for SD only.
Y9-0 I SD or Progressive scan/ HDTV input port for Y data.
Input port for interleaved Progressive Scan data. The LSB is set up
on pin Y0. For 8-bit data input LSB is set up on Y2.
C9-C0 I Progressive Scan/ HDTV input port :4:4 input mode this port is used for
the Cb[Blue/U] data. The LSB is set up on pin C0. For 8-bit data input LSB is
set up on C2.
S9-S0 I SD or Progressive Scan/HDTV input port for Cr [Red/V] data in 4:4:4 input
mode. LSB is set up on pin S0. For 8-bit data input LSB is set up on S2.
RESET
I This input resets the on-chip timing generator and sets the ADV7310/11
into Default Register setting. Reset is an active low signal.
R
SET1,2
I A 3040 Ohms resistor must be connected from this pin to AGND and is used
to control the amplitudes of the DAC outputs.
SCLk I I2C Port Serial Interface Clock Input .
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