Circuit Descriptions and Abbreviation List
EN 119EM5A P/M 9.
Implementation
Figure 9-4 Standby supply circuitry
To apply this on the EM5A (diagram A2): replace switch 'S' by
FET TS7102, coil L by L5101/L5100, diode D by D6111, and C
by C2104.
• Time interval t0-t1: After switching 'on' the TV-set, the
gate of MOSFET TS7102 will be high (max. 15 V due to
zener diode D6105). This will drive the FET into saturation
(U
DS
= 0 V). The DC-voltage U
MAINS
will be transposed
across the primary winding of L5101 (3, 5), resulting in a
linear increasing current through this coil. The voltage
across the co-coupled coil (1, 2) is also positive and will
keep the FET into conductivity via C2101, R3103/3105/
3102 and R3117 for some time. The self-induction of the
coil and the magnitude of the supply voltage (+375 V)
determine the slope of the primary current. The maximum
current is determined by the time the FET stays into
conductance (t0-t1). This time is directly determined by the
voltage across R3108//R3118 (0.7 Ω). This voltage is a
measure of the current and if it exceeds 1.4 V, TS7101 will
be driven into conductivity and consequently connects the
gate of TS7102 to earth. The FET will block. The current is:
1.4 V / 0.7 Ω = 2 A. The voltage across the secondary
winding (8, 9) will be negative, diodes D6111 and D6107
will block.
• Time interval t1-t2: The sudden current interruption in the
primary coil will induce a counter-e.m.f. that wants to
maintain the current. The voltage on the drain of the FET
will increase. The secondary voltage (8, 9) will become
positive and will charge C2104 via D6111. All energy that
was stored in L5101 during t0-t1 will be transferred into the
load. Due to the transformer principle, a voltage will now
be induced in the primary winding (3, 5) and the co-coupled
winding (1, 2). This voltage will be N* U
SEC
(N= winding
ratio). The voltage across the co-coupled coil will be
negative, keeping the FET blocked.
• Time t2: At t2, the current through the secondary coil will
be reduced to zero, as C2104 is no longer charged.
Consequently, the voltages will decay and will change
polarity. The gate of the FET will be again made positive, is
driven into conductivity and the cycle starts again.
Power On Reset (POR)
Figure 9-5 Power On Reset
Via a reset circuit (TS7708) a reset pulse (POR) of 20 ms is
generated for the µP inside the PICNIC and for the ROM. After
'power on', the 3V3 is built up (derived from the 5V2). Transistor
TS7708 blocks and pin 6 of the PICNIC will follow the rising
slope of the power supply. As soon as the power supply is
stabilised, capacitor C2744 will charge (via R3748). When this
voltage reaches 0.6 V (after 20 ms), TS7708 starts to conduct,
and the voltage at pin 6 goes low again. The µP is reset now. If
the PICNIC cannot communicate with the ROM, the 'watchdog'
will generate a reset pulse (on pin 7), which will re-start the
cycle again.
If one of the power supplies is absent (or too low), then a safety
problem can occur in some cases (e.g. a too high temperature
of the stabiliser). To prevent this from happening, the voltage
dividers at the bases of the transistors TS7710 and TS7707 are
calculated such that they will block when above described
situation occurs. In this case, the base of TS7708 is kept 'low'
by the conducting TS7709, until the problem is solved. The µP
receives no POR pulse, and cannot be reset.
5V2 Stabilisation and Feedback
The Standby Power Supply always oscillates at maximum
power. The only limiting factor is the maximum primary current,
which has been pre-set with R3108//3118.
R3113, zener diode D6122, R3124, and R3114 determine
U
OUT
. If the voltage across R3114 exceeds the threshold
voltage of the diode of the optocoupler 7104 (± 1 V) or, in other
words, U
OUT
exceeds 5.2 V, the transistor of the optocoupler
will conduct.
Transistor TS7100 is now driven, and a negative voltage will be
transposed to the emitter of TS7101. When TS7101 conducts,
the gate of the FET is at earth potential, forcing the oscillator
stop. Due to the load, the secondary voltage U
OUT
will
decrease. At a certain voltage, optocoupler TS7104 will block
and the oscillator will start again.
Since there are no capacitors, and there is a high amplification
factor in the feedback circuit, the feedback is ultra-fast. This is
why the ripple on U
OUT
is minimal. The negative supply voltage
(-20 V) used in the feedback circuit, originates from the co-
coupling coil, and is rectified through D6103.
Stabilisation is not effected through duty-cycle control but
through burst-mode of TS7100.
Burst-mode is load dependent. If the power supply is less
loaded, the secondary voltage will have the tendency to
increase more rapidly. If the load on the power supply
increases, then the oscillator stops less often, right up to the
moment that the oscillator is operating continuously: maximum
CL 26532041_062.eps
110402
3103
1K
3105
1K
3113
22R
3124 6122
68R 3V9
RL
7101
6105
15V
3102
1K
3117
47R
3126
10K
3125
15R
7100
3104
47R
3101
STARTUP
V-START
10M
3127
5K6
3120
10R
31063107
1K 1K
2101
2n2
5102
-13V
6111
6103
U
MAINS
U
OUT
2104
2m2
D
S
G
6106
15V
3114
220R
2109 +
2149
6108
3108
//3118
+5V2
8
10
HOT COLD
GND-STB
GND-STB
2
1
5
3
2114
7102
6105
15V
10n
2102
10µ
+
U
A
U
A
U
D
U
D
U
MAIN
I
SEC
I
PRIM
I
PRIM
I
SEC
7103/7104
t
t
t
t
N
.
Usec
ON OFF
t0 t1 t2
5100/5101
3110
2R2
+375V
2111
CL 26532041_075.eps
170402
3752
3753
3751
3790
PICNIC
.6 µP RESET
.7 WD RESET
3V3_FBX
3V3_FBX
3V3_FBX
3747
3748
2744
2743
2V5B
3736
7708
7709
3737
3738
3749
7707
7710
3746
3755
3756
3739
3750
3741
3743
3742
1V5_E
2V5B
3V3_FBX
2V5D
3V3_E
20 ms
2 ms
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