Philips FR980 - Page 42

4-24
QD01,
QD31,
QD51
:
TDA1305T
TDA1305T
SYMBOL | PIN | DESCRIPTION
Vopa
analog
supply
voltage
[Vssa__|_2__| analog ground
TEST1 3 | test input; pin should be connected
to ground (internal pull-down
resistor)
BCK 4 | bit clock input DATA
jws | 5 | word select input
DEEM1 Cpa
1 nF
18 | de-emphasis on/off; fpeem 32 kHz, SYSCLKI
44 kHz and 48 kHz a!
MUSB 19 | mute input (active LOW)
DSMB
20
|
double-speed
mode
input
n.c.
P15]
Vssp
(active
LOW)
ATSB 21 | 12 dB attenuation input
(active LOW)
VOL 22 | left channel output
FILTCL 23 | capacitor for left channel 1st order
filter function should be connected -
between pins 22 and 23 EXTS)
FILTCR 24 | capacitor for right channel 1st order
filter function should be connected
between pins 25 and 24
VOR 25 | right channel output
26. | internal reference voltage for output
channels (0.5Vpp)
Vsso 27 | operational amplifier ground
Vppo 28 | operational amplifier supply voltage
SYSCLKO
Q691 : HD6473257CP10
Sigig- 888 mitts
pe eeeeEe eee
Béeegeteeeseees
9 1
_ =
HD6473257CP10
=
27
Sdidduuee EF
22e22kee Bex
eee Sk REEREEE
PHIL-05429/ Druck 22)
wey
LINEAR INTERPOLATOR
6 x OVERSAMPLING
(SAMPLE—AND-HOLD)
2nd ORDER
NOISE SHAPER
DATA
ENCODER
6 x OVERSAMPLING
(SAMPLE-AND—HOLD) Vppp
2nd ORDER
NOISE SHAPER
DATA
ENCODER
DATA | 6 | data input Vppa CO OS ai
CLKS1 7 {clock selection 1 input
CLKS2 | 8 | clock selection 2 input Vssa Vsso
Vesp | 9 | digital ground TESTI Vref
Vopp 10 | digital supply voltage
: BCK VOR
TEST2 11 | test input; pin should be connected
to ground (internal pull-down ws FILTCR TEST1
resistor) au.
SYSCLKI system clock input DATA FILTCL
nc. 13 | not connected (this pin should be left CLKS1 TDA1305T VOL
open-circuit)
a
i
not
connected
(this
pin
should
be
left
CLKS2
ATSB
Sper aee) Vssp 55MB
Vssp | 15 | digital ground
SYSCLKO | 16 | system clock output Yopb MUSB
DEEM1
17
|
de-emphasis
on/off;
fpeem
32
kHz,
TEST2
DEEM2
FILTCL
44 kHz and 48 kHz
CALIBRATED
CALIBRATED
4-24
Q631 : DSP56009
CLKS1 CLKS2
;
SYSCLKI
ruin [7
SYSCLKO
VssD
16-Bit Bus
FILTCR
CextT2
1 nF
Data ALU
24 x 24 + 56 -» 56-Bit MAC
Two 56-Bit Accumulators.
* Refer to Table 1 for memory
TDA1305T
VSSA
Q691 : HD6473257CP Pin Assignment
Signalname_| vo
eee eee)
control X651 generate (L : stop )
[en
request signal output to Q631
ee ee
reset for Q631 (L: reset )
mute for DAC (L : mute
(ee oe ee ee
reset input (L : reset
system clock ( 16MHz ) generated
system clock ( 16MHz ) generated
CPU mode : Fixed the High
CPU mode : Fixed the High
CPU mode : Fixed the High
2 Fi igh
a
ie) Q
ina
—
ltetels=tel=l*ltel=/lel5| | Teleletelel- || Heft et |5:
fen Ps Pee eS |
| resetforQ601(L:reset)
[control the QRO2’s mute(L: mute) |
| Powersupply(+5VD) sd
Fie eae em eee eee]
[in as a es ee el)
lio oe eee ee
[GND
ignal name
KILLCLK PWRDWN
RDSP002
MUTEIN
L3MODE
L3CLK
L3DATA
vec
37
x J m
O}
> (>) wo
n n
N
4
=
= °
I
I
l
l
|
l
I
I
I
l
| HIT13
| HiT 12
I HIT1
1 HIT10
| Power supply(+5VD) HITS
| CPU moder: Fixedthe High HITS
[PGND fe
ae eee | vss
DTMER | SDA
STROBE |
I
I
l
I
I
I
I
I
I
I
I
I
I
I
LOCK
eae he ee
es ee ee
control the de-emphasis at DAC
attenuate the LFE output level ( L : -10dB)
select data MPEG or other ( H : MPEG )
z
2 RSTDAIO
NI
ANA-SEL
STDBY
DSPCLK
IFACK
(FDATAI
|FDATAO
IFCLK
HITO
HIT1
HIT2
HIT3
HIT4
HITS
HIT6
HIT7
5
27 | AUX1S
AUX2S
IECSEL
HMUTE
) alalalalalala aS = oO NOP o oO
ff a} a] a
= O] ©] N] O] oF
LFEATT
MPEG
67
a