Philips FR980 - Page 43

4-25
QRO02 : TDA1315H
Vssp1 VsSD2 CHMODE UNLOCKFS32 F544 F546
LED DRIVERS eal
(| audio FIFO
, doto +) CONTROL
BIPHASE
MODULATOR Me ir
aaa 'eC eae?
output DEMODULATOR
‘SELECT
DEEM INVALID
12sseL_ 12 SOEN MUTE
[=
| FRAME AND =
{ERROR
{DETECTION
non—oudio dota
YSCLK
aba MICROCONTROLLER
IECINO
IEC
INTERFACE
LCL,
INPUT
CLOCK
AND
TIMING
IECINT
eececr
i
Luove
7
TECSEL CLKSEL RCint —-RCyiy_—“Vret, «= Yppa Vssa SYSCLKO SYSCLKI LADDR upavan “A?
~ ag = = & § G x
Ei cE
R fil © I2SSEL
Vref MUTE
VDDA DEEM
VSSA INVALID
\ECINA COPY
IECINO TDA1315H TESTA
IECSEL
UDAVAIL
1ECO STROBE
IECOEN LDATA
TESTB LCLK
TESTC LMODE
MKA5S89-2
LADOR [22]
S32
FSa4
F548
CHMODE [16 |
Vppp2
Vssp2
is
uNLocK [12 |
cTRLMODE [21]
PHIL-05429/ Druck 23
TDA1315H
| 1 | £029 | PLL loop filter input
decoupling internal reference voltage output
FA ome wenger 2 ee
high sensitivity IEC input
TTL level IEC input
SYMBOL
IECSEL 1UP04 | select IEC input 0 or 1 (0 = IECINO; 1 = IECIN1); this input has an internal pull-up
resistor
lECO 8 OPFH3 | digital audio output for optical and transformer link
IECOEN 9 IUP04 | digital audio output enable (0 = enabled; 1 = disabled/3-state); this input has an
internal pull-up resistor
TESTB | 10 | IPP04 | enable factory test input (0 = normal application; 1 = scan mode)
TESTC 11 IPP04 | enable factory test input (0 = normal application; 1 = observation outputs)
UNLOCK 12 OPP41A | PLL out-of-lock (0 = not locked; 1 = locked); this output can drive an LED
FS32 13 | OPP41A | indicates sample frequency = 32 kHz (active LOW); this output can drive an LED
FS44 | 14 | OPP41A | indicates sample frequency = 44.1 kHz (active LOW); this output can drive an LED
FS48
CHMODE
| 15 | OPP41A | indicates sample frequency = 48 kHz (active LOW); this output can drive an LED
16 | OPP41A | use of channel status block (0 = professional use; 1 = consumer use); this output
can drive an LED
Vppp2 digital supply voltage 2
Vsspe2 18 E009 | digital ground 2
RESET initialization after power-on, requires only an external capacitor connected to Vopp;
this is a Schmitt-trigger input with an internal pull-down resistor
PD IPP04 | enable power-down input in the standby mode (0 = normal application; 1 = standby
mode)
select microcontroller/stand-alone mode (0 = microcontroller; 1 = stand-alone); this
input has an internal pull-up resistor
microcontroller interface address switch input (0 = 000001; 1 = 000010)
IUP04
°
4 BY ion =
e)
oO m nN x
ho
LADDR IPP04
iPPOS
iPPOS
\OF24
(DP4
OPF23
ipPOa
PP41A | copyright status bit (0 = copyright asserted; 1 = no copyright asserted); this output
can drive an LED
validity of audio sample input/output (0 = valid sample; 1 = invalid sample); this pin
has an internal pull-down resistor
OPFas
audio mute input (0 = permanent mute; 1 = mute on receive error); this pin has an
LCLK 24
UDAVAIL 27
28
OPY
fe)
INVALID loD24
=
3
internal pull-up resistor
select auxiliary input or normal input in transmit mode
IPP04 | auxiliary serial data input; 12S-bus
#SSEL 33
34
|UP04
|OF24
serial audio data input/output; [?S-bus
1OF24 | word select input/output; 12S-bus
1OF29 __| serial audio clock input/output; I2S-bus
IUP04 | serial audio output enable (0 = enabled; 1 = disabled/3-state); this input has an
internal pull-up resistor
IPPO9 | system clock input (transmit mode)
OPFA3_ | system clock output (receive mode)
digital ground 1
E008 digital supply voltage 1
|UP04 | select system clock (0 = 384f,; 1 = 256f,); this input has an internal pull-up resistor
E029 integrating capacitor output
n
x a om) Cc
z18/S = Bim S/S) Sale
& = SE} 8| Sl &|S
(a m
x > @| > A
CK
SYSCLKI
SYSCLKO
39
40
fo
v
CLKSEL
RCint
sk g
a
g |g
g
44
on bP T=
4-25
QK01 : SAA7367
Vssa VretR TESTB STDB
operational
amplifier
operational
amplifier
> REFERENCE
VOLTAGE
lh ge
GENERATOR
CLOCK
GENERATION
ANI
CONTROL,
ame S Vppp
Vpace K SIGMA- Vesp
DELTA
MODULATOR DECIMATION FILTER
REFERENCE TIMING
let CURRENT GENERATOR STAGE1| STAGE2
GENERATOR COMB |3 HALF-BAND
SIGMA- FILTER | FILTERS
DELTA
VDACN MODULATOR
= SAA7367
HIGH-PASS
BOL — OvLD
BIL
ier
Sg
REFERENCE
>
—
VOLTAGE
spo
GENERATOR
SYMBOL
SFOR
STDB
OVLD
CKIN
Vppp
Vssp
operational
amplifier operational SCK
amplifier
Vppa Vref HPEN TEST! 5. aye SFOR
SAA7367
DESCRIPTION
TTL level input; in normal mode this input selects the serial interface output format; output
format is selected as follows:
SFOR = HIGH selects Format 1
SFOR = LOW selects Format 2 (similar to I2S)
schmitt-trigger input; in normal mode, this input is used to select standby mode:
STDB = HIGH selects normal operation
STDB = LOW selects standby mode (low power consumption)
TTL level output; in normal mode this output indicates whether the internal digital signal is
within 1 dB of maximum; if so, the output will go HIGH for 131072 clock cycles (approximately
11 ms); in standby mode this output is forced LOW
CMOS level input; system clock input; nominally clocked at 256f,
digital supply voltage (4.5 to 5.5 V)
digital ground
als
o
N TTL level output (3-state); in normal mode this pin outputs data from the serial interface; in
standby mode, this output is high impedance
TEST1
HPEN
TESTB
sws
TTL level input/output; serial interface word select signal; in master mode (SLAVE = LOW),
this pin outputs the serial interface word select signal; in slave mode (SLAVE = HIGH), this pin
is the word select input to the serial interface; in standby mode (STDB = LOW) this pin is
always an input (high impedance); for polarity: see Table 1
TTL level input/output; in master mode (SLAVE = LOW) the pin outputs the serial interface bit
clock; in slave mode (SLAVE = HIGH) this pin is the input for the external bit clock; data on
SDO is clocked out on the HIGH-to-LOW transition of SCK; the data is valid on the
LOW-to-HIGH transition
Test 1; TTL level input with internal pull-down; in slave mode (slave = HIGH), this pin is used
to select extra serial interface formats (see Table 2)
TTL level input; this input is used to enable the internal high-pass filter when HIGH; in
scan-test mode (TESTB = LOW and TEST1 = LOW) this pin functions as “scan chain c' input
12 Test B; CMOS level input with internal pull-up; in normal applications, this input should be left
HIGH
13 analog ground; this pin is internally connected to Vsg via the on-chip substrate contacts
14 current reference generator output; 33 kQ in parallel with 22 nF is connected from this pinto
Vssa
15 tight channel analog reference output voltage (%Vppa)
16 buffer operational amplifier inverting input for right channel
buffer operational amplifier output for right channel
negative 1-bit DAC reference voltage input, connected to 0 V
19 positive 1-bit DAC reference voltage input, connected to +5 V
buffer operational amplifier output for left channel
buffer operational amplifier inverting input for left channel
left channel analog reference output voltage (%Vppa)
23 analog supply voltage (4.5 to 5.5 V)
PCS 98 #20