15-5
15-5
EN29LV320A IC Specification
PRODUCT SELECTOR GUIDE
A023VL92NE rebmuN tcudorP
Speed Option
-70 -90
Max Access Time, ns (t
acc
)
70 90
Max CE# Access, ns (t
ce
)
70 90
Max OE# Access, ns (t
oe
)
30 35
Notes:
1. Vcc=3.0 – 3.6 V for 70ns read operation
BLOCK DIAGRAM
WE#
CE#
OE#
State
Control
Command
Register
Erase Voltage Generator
Input/Output Buffers
Program Voltage
Generator
Chip Enable
Output Enable
Logic
Data Latch
Y-Decoder
X-Decoder
Y-Gating
Cell Matrix
TimerVcc Detector
A0-A20
Vcc
Vss
DQ0-DQ15 (A-1)
Address Latch
Block Protect Switches
STB
STB
RY/BY#
32M FLASH USER MODE TABLE
DQ8-DQ15
Operation CE# OE# WE#
RESET
#
WP#/AC
C
A0-
A20
DQ0-
DQ7
BYTE#
= V
IH
B
BYTE#
= V
IL
B
Read L L H H L/H A
IN
B D
OUT
B D
OUT
B
Write L H L H (Note 1) A
IN
B D
IN
B D
IN
B
Accelerated
Program
L H L H V
HH
A
IN
B D
IN
B D
IN
B
DQ8-
DQ14=
High-Z,
DQ15 =
A
-1
CMOS Standby
V
cc
B ±
0.3V
X X
V
cc
B ±
0.3V
H X High-Z High-Z High-Z
TTL Standby H X X H H X High-Z High-Z High-Z
Output Disable L H H H L/H X High-Z High-Z High-Z
Hardware Reset X X X L L/H X High-Z High-Z High-Z
Sector (Group)
Protect
L H L V
ID
B
L/H
SA,
A6=L,
A1=H,
A0=L
(Note 2) X X
Sector
Unprotect
L H L V
ID
B
(Note 1)
SA,
A6=H,
A1=H,
A0=L
(Note 2) X X
Temporary
Sector
Unprotect
X X X V
ID
B (Note 1) A
IN
B (Note 2) (Note 2) High-Z
L=logic low= V
IL
B, H=Logic High= V
IH
B, V
ID
B =V
HH
=11 ± 0.5V = 10.5-11.5V, X=Don’t Care (either L or H, but not floating ),
SA=Sector Addresses, D
IN
B=Data In, D
OUT
B=Data Out, A
IN
B=Address In
Notes:
1. If WP#/ACC =
V
IL
B
, the two outermost boot sectors remain protected. If WP# / ACC = V
IH
B
, the outermost boot sector
protection depends on whether they were last protected or unprotected. If WP#/ACC =
V
HH
B, all sectors will be
unprotected.
2. Please refer to “Sector/Sector Group Protection & Chip Unprotection”, Flowchart 7a and Flowchart 7b.