Philips LPC213 Series

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Overview

Function Description
Important Technical Specifications
Usage Features
Maintenance Features

The Philips Semiconductors UM10120, Volume 1: LPC213x User Manual, describes a family of 16/32-bit ARM7TDMI-S microcontrollers, including the LPC2131, LPC2132, LPC2134, LPC2136, and LPC2138. These microcontrollers are designed for embedded applications requiring high performance, low power consumption, and miniaturization, such as access control, point-of-sale, communication gateways, protocol converters, soft modems, voice recognition, low-end imaging, industrial control, and medical systems.

Function Description

The LPC213x microcontrollers integrate an ARM7TDMI-S CPU with real-time emulation and embedded trace support. They feature on-chip Flash memory for program storage and static RAM (SRAM) for code and data. The architecture includes an ARM7 Local Bus for memory interface, an AMBA Advanced High-performance Bus (AHB) for the interrupt controller, and a VLSI Peripheral Bus (VPB) for on-chip peripheral functions. The processor operates in little-endian byte order.

The core supports both a standard 32-bit ARM instruction set and a 16-bit THUMB instruction set, which offers improved code density with minimal performance penalty. The on-chip Flash memory supports In-System Programming (ISP) and In-Application Programming (IAP) for flexible firmware updates and data storage. A boot loader manages initial operations and programming.

The Memory Accelerator Module (MAM) optimizes Flash memory access for the ARM processor, utilizing a single Flash bank and incorporating Prefetch, Branch Trail, and Data buffers to minimize CPU fetch stalls.

The Vectored Interrupt Controller (VIC) manages 32 interrupt request inputs, classifying them into FIQ (highest priority), vectored IRQ (middle priority), and non-vectored IRQ (lowest priority). This allows dynamic assignment and adjustment of interrupt priorities.

The System Control Block includes a crystal oscillator, external interrupt inputs, memory mapping control, a Phase Locked Loop (PLL), power control, reset functions, a VPB Divider, and a Wakeup Timer. The PLL generates the CPU clock (CCLK) from an external oscillator, while the VPB Divider controls the clock rate for peripheral devices (PCLK). The Wakeup Timer ensures system stability after power-on or wakeup from power-down modes.

General Purpose Input/Output (GPIO) ports provide flexible digital I/O with individual direction control and separate set/clear registers.

The Universal Asynchronous Receiver/Transmitter (UART) modules (UART0 and UART1) provide serial communication with 16-byte FIFOs, programmable baud rates, and support for software flow control. UART1 additionally includes standard modem interface signals (LPC2134/6/8 only).

The I2C interfaces (I2C0 and I2C1) are compliant with the standard I2C-bus specification, supporting master, slave, or master/slave modes, arbitration, programmable clock rates, and bidirectional data transfer.

The Serial Peripheral Interface (SPI0) is a full-duplex synchronous serial interface, supporting master and slave operations with 8 to 16 bits per transfer. The SSP Controller (SPI1) is a more versatile synchronous serial port, compatible with Motorola SPI, 4-wire TI SSI, and National Semiconductor Microwire buses, featuring 8-frame FIFOs and 4 to 16-bit frames.

Timer/Counter modules (TIMER0 and TIMER1) offer 32-bit counting with programmable prescalers, capture channels for input signal transitions, and match registers for generating interrupts or controlling external outputs.

The Pulse Width Modulator (PWM) is based on the Timer block, providing up to 6 single-edge or 3 double-edge controlled PWM outputs with flexible pulse period and width control.

Analog-to-Digital Converters (ADC) are 10-bit successive approximation converters with 8-pin input multiplexing, power-down mode, burst conversion, and optional hardware-triggered conversions. The LPC2134/6/8 devices include two ADCs.

The Digital-to-Analog Converter (DAC) (LPC2132/4/6/8 only) is a 10-bit converter with a resistor string architecture and buffered output, featuring power-down mode and selectable speed/power trade-off.

The Real Time Clock (RTC) measures time, supporting calendar and clock functions, with ultra-low power design for battery-powered systems. It can be clocked by a dedicated 32 kHz oscillator or a programmable prescaler from the VPB clock.

A Watchdog Timer provides system reset if the program enters an erroneous state, with a programmable time-out interval.

Important Technical Specifications

CPU: 16/32-bit ARM7TDMI-S with real-time emulation and embedded trace.
Flash Memory: 32 kB, 64 kB, 128 kB, 256 kB, or 512 kB on-chip Flash program memory. 128-bit wide interface/accelerator for 60 MHz operation. Minimum 10,000 erase/write cycles, 10 years data retention.
SRAM: 8 kB, 16 kB, or 32 kB on-chip static RAM.
I/O Pins: Up to 47 5V tolerant general purpose I/O pins in LQFP64 package. Up to 9 edge or level sensitive external interrupt pins.
CPU Clock: 60 MHz maximum from programmable on-chip PLL. Settling time of 100 µs.
Oscillator: On-chip integrated oscillator (1 MHz to 30 MHz with external crystal, or 1 MHz to 50 MHz with external oscillator). PLL input clock range: 10 MHz to 25 MHz.
A/D Converters: One (LPC2131/2) or two (LPC2134/6/8) 8-channel 10-bit ADCs. Conversion times as low as 2.44 µs per channel. Measurement range 0 to 3V.
D/A Converter: Single 10-bit DAC (LPC2132/4/6/8 only).
Timers: Two 32-bit timers/external event counters with four capture and four compare channels each.
PWM: Unit with six outputs.
RTC: Low power Real-time clock with independent power and dedicated 32 kHz clock input.
Serial Interfaces: Two UARTs (16C550), two Fast I2C (400 kbit/s), SPI, and SSP.
Interrupt Controller: Vectored interrupt controller with configurable priorities and vector addresses.
Power Supply: 3.0 V to 3.6 V (3.3 V ± 10%) CPU operating voltage.
Power-On Reset (POR) and Brown-Out Detection (BOD) circuits.

Usage Features

Code Execution: 32-bit code execution at maximum clock rate, with 16-bit Thumb Mode for code size reduction.
In-System/In-Application Programming (ISP/IAP): On-chip boot-loader software for Flash programming. Single Flash sector or full chip erase in 400 ms, 256 bytes programming in 1 ms.
Real-time Debugging: EmbeddedICE® and Embedded Trace interfaces with on-chip RealMonitor™ software for high-speed tracing.
Power Saving Modes: Idle and Power-down modes. Individual enable/disable of peripheral functions and peripheral clock scaling for power optimization. Processor wake-up from Power-down via external interrupt or Real-time Clock.
Flexible Pin Configuration: Pin Connect Block allows selection of multiple functions for device pins.
Interrupt Management: Vectored Interrupt Controller allows dynamic priority assignment for 32 interrupt sources.
Clocking Flexibility: Programmable PLL for CPU clock and VPB Divider for peripheral clock.
GPIO Control: Individual direction control, separate set/clear registers for output pins.
UART Features: 16-byte FIFOs, programmable baud rate, software flow control. UART1 includes modem interface signals for LPC2134/6/8.
I2C Modes: Master, slave, or master/slave operation with arbitration and programmable clock rates.
SPI/SSP Modes: Full duplex synchronous serial communication, master/slave operation, 8 to 16-bit frames. SSP is compatible with various serial bus protocols.
Timer/Counter Functionality: Interval timing, pulse width demodulation, free-running timer, capture events, match events for interrupts or output control.
PWM Outputs: Single-edge or double-edge controlled PWM outputs with flexible pulse period and width.
ADC Conversions: Burst mode for single or multiple inputs, optional hardware-triggered conversions.
RTC Functions: Calendar and clock functions, low power operation for battery-backed systems.
Watchdog Timer: Programmable time-out to reset the microcontroller in case of software errors.

Maintenance Features

Flash Memory Reliability: Minimum 10,000 erase/write cycles and 10 years of data retention.
Boot Loader: Provides initial programming and re-programming capabilities for Flash memory.
Code Read Protection (CRP): Software-enabled feature to protect application code from observation, disabling JTAG debug port and certain ISP commands.
Brown-Out Detection (BOD): Two-stage monitoring of VDD voltage to assert an interrupt or reset the device, preventing unreliable operation due to low voltage.
RealMonitor: Configurable software module for real-time debugging without halting or resetting the system, allowing time-critical interrupt code to continue execution.
JTAG Interface: Used for debugging and Flash programming.
Error Correction Code (ECC): Flash memory is equipped with ECC for single-bit error correction, ensuring data integrity. Data must be written in groups of 4 bytes for proper ECC operation.