PIN ASSIGNMENTS FOR 48-LEAD TSOP
Y- D e coder
I/O Buffers and Data Latches
360 ILL B1.2
Address Buffer & Latches
X-Decoder
DQ
15
- DQ
0
Memory Address
OE#
CE#
WE#
SuperFlash
Memory
Control Logic
FUNCTIONAL BLOCK DIAGRAM
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
NC
NC
NC
NC
NC
NC
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A16
NC
V
SS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
DD
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
V
SS
CE#
A0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
360 ILL F01.2
Standard Pinout
To p Vi e w
Die Up
SST39LF200A/400A/800A
SST39VF200A/400A/800A
SST39LF/VF200A
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
NC
NC
NC
NC
NC
A17
A7
A6
A5
A4
A3
A2
A1
SST39LF/VF400A
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
NC
NC
NC
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
SST39LF/VF800A SST39LF/VF200A
A16
NC
V
SS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
DD
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
V
SS
CE#
A0
SST39LF/VF400A
A16
NC
V
SS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
DD
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
V
SS
CE#
A0
SST39LF/VF800A
PIN DESCRIPTION
Symbol Pin Name Functions
A
MS
1
-A
0
Address Inputs To provide memory addresses. During Sector-Erase A
MS
-A
11
address lines will select the
sector. During Block-Erase A
MS
-A
15
address lines will select the block.
DQ
15
-DQ
0
Data Input/output To out p u t data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.
CE# Chip Enable To activate the device when CE# is low.
OE# Output Enable To gate the data output buffers.
WE# Write Enable To control the Write operations.
V
DD
Power Supply To provide power supply voltage: 3.0-3.6V for SST39LF200A/400A/800A
2.7-3.6V for SST39VF200A/400A/800A
V
SS
Ground
NC No Connection Unconnected pins.
1. A
MS
= Most significant address
A
MS
= A
16
for SST39LF/VF200A, A
17
for SST39LF/VF400A, and A
18
for SST39LF/VF800A
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