Philips PM 3266 - 3.2.5. Delayed time-base generator; 3.2.6. X deflection selector and alternate time-base logic

118
3.2.5.2.
Delayed
time-base
end
of the sweep
detection
circuit
This circuit
prevents
the sweep
gating
logic
from
responding
to trigger
pulses
before
the time-base
capacitor
has
fully
discharged.
The
sawtooth
output
is
applied
to point
7 of
SR flip-flop
D902.
At
the
end
of the
time-base
sweep,
output
2 of
the SR
flip-flop
D902
will
be
"high"
and
output
3
will
be
"low".
These
logic
levels
are
transferred
to
pins
5
and 4
respectively
of D901
irrespective
of
the
state of
the
comparator
D1303.
As
a result,
the
Q
output
becomes
"low"
and
the timing
capacitors
are
discharged
via
VI
311,
since
the
flip-flop
D902
is
not
reset
until
the end
of the
main
time-base
sweep
(D902-15on
MTB
connected via
a differential
network
to D902-5
on DTB).
This
situation
will
persist
until
the
next
sweep
of
the
time-base.
If
the
main
time-base
sweep
is
completed
before
the end
of
the
delayed
time-base,
the
R and
S
inputs
(5
and
4)
of D901
are switched
over
and
the delayed
time-base
capacitors
also
are
discharged.
The
system
can
now
be triggered
again.
3.
2. 5.
3.
Delay
time
function
The
function
of
the DELAY
TIME
potentiometer
R1
is
to
provide
an
adjustable
d.c.
voltage
for
comparison
with
the sweep
voltage
of the
main
time-base
generator.
This
comparison
is
then
used
to
start the
delayed
time-base
generator
at
a
pre-determined
time
during
the
sweep
of the
main
time-base.
The
DELAY-TIME
potentiometer
R1
is
a 10-turn
front
-panel
control.
3.2.5.
4. Comparator
circuit
and sweep
gating
logic
The
comparator
consist
of an
integrated
circuit
D1
303. Transistor
(points 6-7-8)
is
a constant
-current
source
for the
transistors
(points
1
-2-3
and
points
3-4-5)
of
a differential
amplifier.
The
d.c.
voltage
set
by the DELAY
TIME
potentiometer
R4
is
fed
to the base
of
transistor
(points
3-4-5).
The
sawtooth
voltage
of
the
main
time-base
generator
is fed
to the base of
the other
transistor.
As
soon
as
the
amplitude
of the
sawtooth
exceeds
the set d.c.
voltage,
a
high
level is passed
from D1
303,
pin
5,
to
input
4
of
m^ter-slave
flip-flop D901
( R input)
,
and
a low level
from D 1
303,
pin
1 to S input
5 of D901
.
The
Q
output
on point
3 will then
be high,
with as
result that VI
304 and the
time-base
capacitor discharge
switches
VI
309
and VI
31 1 will
be turned
off.
This is
the situation in
the MTB
position
of the switch
S21
.
In
positions A,
B or EXT
of
delayed
time-base
trigger selection
switch
S21, point 4
of D901
is always
low via
S21
The
delayed
time-base
then
starts first upon
receipt
of trigger
pulses
on
clock
input
6,
after the
S input
has
dropped
to
the low
level.
3,2.6.
X deflection
selector
and
alternate
time-base
logic
Depending
on
the
selected
position of
X deflection
source
selector switch
S2, the circuit
provides
for X
deflection
by the main
time-base signal,
the
delayed
time-base signal,
a signal from
an external
source
or
X
deflection
by
one of
the internal
signals derived
from
channel A,
channel B or the
mains voltage.
There is
also the
possibility
to select, the
main
and delayed
time-base alternately.
MAIMD
EXT X-DFFL
ALT
T B
DFL’D
TB
SEPARATION
MAIN
T'ME BASc
TO
X--INAL
AMHMHI-H
MAT96
Fig.
3.11. X deflection
selector
and alternate time-base
logic
main