PTC PT6315 - Page 13

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VFD Driver/Controller IC PT6315
PT6315 v2.0 Page 13 Sep. 2002
SCANNING AND DISPLAY TIMING
The Key Scanning and display timing diagram is given below. One cycle of key scanning consists of 2 frames.
The data of the 16 x 2 matrix is stored in the RAM.
Internal Operating Frequency (fosc) = 224/T
Figure 12: PT6315 Scanning & Display Timing Diagram
1 2 8
9 10 16
SGn
G1
G2
G3
T=500us
DISPLAY
Key Scan Data
Gn
1 Frame=Tx (n +1) DISPLAY
T
Note: T is the width of Segment only