Quectel BC68 Hardware Design

GSM/GPRS Module Series
M66 Hardware Design
M66_Hardware_Design Confidential / Released 33 / 80
Hardware flow control is disabled by default. When hardware flow control is required, RTS and CTS
should be connected to the host. AT command AT+IFC=2,2 is used to enable hardware flow control. AT
command AT+IFC=0,0 is used to disable the hardware flow control. For more details, please refer to the
document [1].
The Debug Port:
 DBG_TXD: Send data to the COM port of computer.
 DBG_RXD: Receive data from the COM port of computer.
The Auxiliary UART Port:
 TXD_AUX: Send data to the RXD of DTE.
 RXD_AUX: Receive data from the TXD of DTE.
The logic levels are described in the following table.
Table 7: Logic Levels of the UART Interface
Table 8: Pin Definition of the UART Interfaces
Parameter
Min.
Max.
Unit
V
IL
0
0.25×VDD_EXT
V
V
IH
0.75×VDD_EXT
VDD_EXT +0.2
V
V
OL
0
0.15×VDD_EXT
V
V
OH
0.85×VDD_EXT
VDD_EXT
V
Interface
Pin Name
Pin No.
Description
UART Port
TXD
17
Transmit data
RXD
18
Receive data
DTR
19
Data terminal ready
RI
20
Ring indication
NOTE
Quectel
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Quectel BC68 Specifications

General

Brand	Quectel
Model	BC68
Category	Control Unit
Language	English