Quectel EG21-G - Page 46

LTE Module Series
EG21-G Hardware Design
EG21-G_Hardware_Design 45 / 100
PCM_CLK
PCM_SYNC
PCM_OUT
MSB
LSB
MSB
125us
1 2 256255
PCM_IN
MSB
LSBMSB
Figure 22: Primary Mode Timing
PCM_CLK
PCM_SYNC
PCM_OUT
MSB
LSB
PCM_IN
125us
MSB
1 2 3231
LSB
Figure 23: Auxiliary Mode Timing
The following table shows the pin definition of PCM and I2C interfaces which can be applied on audio
codec design.
Table 14: Pin Definition of PCM and I2C Interfaces
Pin Name
Pin No.
I/O
Description
Comment
PCM_IN
24
DI
PCM data input
1.8V power domain
PCM_OUT
25
DO
PCM data output
1.8V power domain