14
TITLE
PROJECT
Lorry XU
Woody WU
CHECKED BY
DRAWN BY
OF
A
6
5
4
32
1
SHEET
A
B
C
D
123456
D
C
B
Quectel Wireless Solutions
SIZE
VER
14
1.0
DATE
2019/12/5
EG21-G
A2
Reference Design
Reserved Test Points
1. Test points for both USB and debug UART interfaces are reserved for software debugging.
2. Test points for USB interface also can be reserved for firmware upgrade.
Indicators
2. For more details about NET_MODE and NET_STATUS, please refer to
Notes:
1. The STATUS is an open drain output pin, and its drive current is less than 1mA.
Other Designs
3. Junction capacitance of ESD protection devices on USB data lines should be less than 2pF.
Notes:
3. If the current consumption is required as low as possible when the device is in sleep, replace the power supply of indicators with controllable one.
4. The module's debug UART interface supports 1.8V power domain,
Turn off the power when the module enters sleep mode.
1. It is recommended to reserve USB_BOOT design.
Notes:
2. USB_BOOT is kept open by default.
When it is at high level, the module will enter download mode.
A level translator should be used if the power domain of customers' application is 3.3V.
Quectel_EG21-G_Hardware_Design.
USB_BOOT Interface
D1307
SD12
D1306
ESD9L5.0ST5G
D1305
ESD9L5.0ST5G
D1309
ESD9X3.3ST5G
D1310
ESD9X3.3ST5G
Q1303
DTC043ZEBTL
R1304
2.2K
D1302
Q1302
DTC043ZEBTL
R1303
2.2K
D1301
D1311
ESD9X3.3ST5G
1
2
J1301
R1306
4.7K
D1304
ESD9X3.3ST5G
4
5
6
3
2
1
7
8
9
J1302
Connector
R1307
2.2K
D1312
[3,5,14]
VBAT
[3,4]
PWRKEY
[3]
USB_DP_TEST
[3]
USB_DM_TEST
[3,4]
USB_VBUS
[3]
DBG_RXD
[3]
DBG_TXD
[3]
NET_STATUS
DC_5V
[3]
NET_MODE
DC_5V
[3,4,5,6,11,13]
VDD_EXT
[3]
USB_BOOT
DBG_TXD_FC20
[3]
STATUS
VBAT
To Previous Page
Loading...
Need help?
General
