Radio Shack 26-3801 - Page 32

z8
TECHNICAL
DESCRIPTION
As
described
below,
the
technical
description
of
the Model
100
main
P.W.
board
is
divided
into 16
sections.
1.
LSIs
2
.
MEMORY
3.
ADDRESS
DECODING &
BANK
SELECTION
4.
MEMORY
MAP
5.
I/O
MAP
&
I/O
PORT
DESCRIPTION
6
.
KEYBOARD
7.
CASSETTE
INTERFACE CIRCUIT
8.
PRINTER
INTERFACE CIRCUIT
9.
BAR
CODE
READER INTERFACE
CIRCUIT
10.
BUZZER
CONTROL
CIRCUIT
11.
SYSTEM
BUS
12.
LCD
INTERFACE
CIRCUIT
13.
CLOCK
CIRCUIT
14.
SERIAL
INTERFACE
15.
POWER
SUPPLY
&
AUTO
POWER OFF CIRCUIT
16.
RESET
CIRCUIT
1.
LSIs
(1)
MSM80C85ARS
(CPU)
1-chip,
8-bit
C-MOS
Process Microprocessors
The
MSM80C85ARS
(80C85)
is a complete 8-bit parallel
Central
Processing
Unit (CPU) . Its instruction
set
is
100%
software
compatible with
the
8080A
microprocessor,
and
it is designed to improve the
present
8080A's
performance with
a
higher
system speed.
The
80C85 uses
a multiplexed
data bus.
The address
is
split
between
the 8-bit
address
bus
and the
8-bit
data
bus
.
For
the Model
100,
the data
bus and address bus are
separated
by Ml (TC40H373P:
octal "D" type latch)
.
The driveability
of the bus
line
is
increased by M2
(TC40H24P: octal
bi-directional
b-
(TC40H244P: octal
buffer/driver).
(TC40H24P: octal
bi-directional
bus buffer) and M2i