Radio Shack 26-3801 - Page 42

TABLE
7 A.C.
CHARACTERISTICS
T
A
-
40°
C
to
+85°
C;
V
cc
-
5V ±10%; V
ss
-
0V
~&
Symbol
tCYC
t>
tr.
«f
<XKR
«XKF
«AC
<ACL
»AO
<AFR
*AL
«ALL
<ARY
«CA
tec
«CL
tQW
*HABE
<HABF
'HACK
*HDH
'HDS
«INH
<INS
«LA
<LC
'LCK
«LDR
'LOW
«LL
<LRY
tRAE
tRD
«RV
«RDH
«RYH
«RYS
«WD
l
WDL
Parameter
CLK Cycle
Pe'iod
CLK Low
Tims
—
Standard
150 pF
Loading
CLK
High
Time
-
Standard
150
pF
Loading
CLK Rise and Fall
Time
X,
Rising
to CLK Rising
X, Rising
to CLK Falling
Ai_u
Valid
to Leading
Edge
of
Control"'
Ao_»
Valid
to
Leading
of
Control
A,,_u
Valid
to Valid
Data In
Address Float after
Leading
Edge of
READ (INTA)
A,_i,
Valid before
Trailing
Edge of
ALE*
1
'
A,_, Valid
before Trailing
Edge of
ALE
READY Valid
from
Address Valid
Address
(A,—
A,j)
Valid after
Control
Width of
Control Low
(RD, WR,
INTA) Edge of ALE
Trailing
Edge of Control
to
Londing
Edge
of
ALE
Dota Valid
to
Trolling
Edge of
WRITE
HLOA
to Bus Enable
Bus Float
after
HLOA
HLDA
Valid
to
Trailing
Edge of
CLK
HOLD Hold Time
HOLD Setup Time
to
Trailing
Edge of
CLK
INTR Hold Time
INTR, RST, and TRAP
Setup Time
to Falling
Edge
of
CLK
Address
Hold Time after
ALE
Trailing Edge of
ALE
to
Leading
Edge of Control
ALE Low during
CLK
High
ALE to
Valid
Data
during Read
ALE to Valid
Data
during
Write
ALE Width
ALE to READY
Stable
Trailing Edge of
READ to
Re-Enabling
of
Address
READ
(or
INTA)
to Valid
Data
Control Trailing
Edge to Leading
Edge of Next Control
Data
Hold Time
After
READ INTA
(7)
READY Hold Time
READY Setup Time
to Leading
Edge of CLK
Data
Valid
After Trailing
Edge of
WRITE
LEADING Edge of
WRITE
to Data Valid
Min.
Max.
Unit
320
2000 ns
80
ns
ns
120
ns
30 ns
30 120
ns
30 150
ns
270
ns
240
ns
575
ns
ns
115
ns
90
ns
220
ns
120
ns
400
ns
50
ns
420
ns
210 ns
210 ns
110
ns
ns
170
ns
ns
160
ns
100
ns
130
ns
100
ns
460
ns
200 ns
140
ns
110 ns
150
ns
400
300 ns
ns
ns
ns
110
ns
100 ns
40 ns
Notes:
1.
A,—
An
address Specs
apply
to IO/M,
So,
and
S,
except A,-A,j are
undefined
during T
4
—
T«
of OF cycle
whereas
IO/M,
So.
and
Si
are
stable.
2.
Test
conditions:
tcYC
"
320ns
C|_
»
1
50
pF
3.
All timings are
measured
at output voltage V
t
»
0.8V,
Vh
»
2.2V and
1.5V
with 20ns
rise
and tail time on
inputs.