96
(3)
HD6402(UART)
C-MOS
UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER
(a)
Description
The HD-6402
is
a
CMOS/LSI
subsystem for
interfacing computers or
microprocessors
to
an
asynchronous serial
data channel.
The
receiver
converts
serial start, data, parity
and
stop
bits
to
parallel data verifying proper
code transmission,
parity, and
stop bits. The
transmitter
converts parallel data
into serial
form
and automatically adds start, parity,
and
stop
bits.
The data word length can be
5, 6,
7 or
8
bits. Parity may be
odd or
even.
Parity
checking
and
generation can
be
inhibited.
The stop bits
many be one or
two or one
and
one-half
when transmitting
5
bit code.
The
HD-6402
can
be used in a wide range
of
applications including modems, printers,
peripherals
and remote
data aquisition
systems.
CMOS/LSI
technology
permits operation
clock
frequencies up to 2.0 MHz
(125K
Baud)' an
improvement of
10
to
1
over
previous
PMOS
UART
designs. Power requirements, by
comparison,
are reduced from
300
mW
to
10
raW.
Status logic
increases
flexibility
and simplifies
the user interface.
CONTROL
WORD
CHARACTER
FORMAT
TOP
VIEW
v
Cc
C
!•
40
3 TRC
NC
C
J
39
3
EPE
GNO
C
3 M
3 CLS1
RRO
C
4 37
3 CLS2
RSRt
C
S 3f
3 sas
R8R7
C 1
3S
3
PI
RIM
C
7
34
3
CRl
RBR5
C • 33 3
TBRI
RBR4 C S 32
3 TBR7
R8R3
C
10 31 3 TBRI
nam c
11 30
3
TBRS
RBR1
C
12
2»
3 TBR4
PE
C
1}
21
3
TBR3
rt
c
u
27
3
TBR2
OE C
13
2S
3
TBRI
SPO c
1!
2S
3
TRO
RRCC 17 24
3
TRE
DRR
C
11
23 3
TBRL
OR
C
11 22 3
T8RE
RRI C 20
21 3 MR
Fig. 14 Pin Layout
c c
L L
P
E S
S
S
I f> B START
DATA
PARITY STOP
2 1
E. S
BIT
BITS
SIT BITS
a
1
I
1
1
!
1
1
1
1
! 1
1 1
1
1
I
1
OOD
ODD
EVEN
EVEN
NONE
NONE
•OOO
ODD
EVEN
EVEN
NONE
NONE
OOD
ODD
EVEN
EVEN
NONE
NONE
ODD
ODD
EVEN
EVEN
NONE
NONE
Table
10
Control
Word Format
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