Radio Shack Quick Printer II Technical Reference Manual

DYNAMIC
MEMORY
CONTROL
One
of
the
most important
chips in
the Color
Computer
is
the
MC6883
(U10).
This
chip is
a
synchronous
address
multiplex-
er,
sometimes
referred
to
as
SAM.
SAM
generates
all of
the
system
timing
for
the
Color
Computer
and
all
of the
device
selection.
In
addition,
it generates
video
address
lines
and
multiplexes
these
with
the
CPU
address
lines
for
the dynamic
memory.
A
funtional
block
diagram
of
the
MC6883
is
shown
in
Figure
5.
To control
this
versatile
chip,
a 16-bit
control
register
is used.
These
sixteen
bits are
divided
as follows:
VDG
ADDRESSING
MODE
-
3 bits
VDG
ADDRESS
OFFSET
-
7
bits
PAGE
SWITCH
-
1
bit
MPU
RATE
-
2 bits
MEMORY
SIZE
-
2 bits
MAP
TYPE
-
1
bit
To
set
one of
these
bits,
an odd
address
in the
range
of
FFC0-
FFDF is
written
to. To
clear
one
of
the bits,
an even
address
in
the same
range
is
written
to. The
Memory
Map
(page
10)
shows
the
breakdown
of
these
bits.
The Color
Computer
timing
chain
begins
with
the 14.31818
MHz
oscillator
composed
of
R43,
X1, C51,
C4,
and the
internal
oscillator
in the
MC6883.
This is
a series
resonant
circuit.
C51
and
C4 are
used
to exactly fix
the frequency
of
the
oscillation.
C4
is a variable
capacitor
which
allows
minor
frequency
adjustments
to
compensate
for
device
variation.
C4
should be
adjusted
to give
a video
clock frequency
of
exactly
3.579545
MHz.
R43 is
used to
control
the voltage
output of
the oscillator.
From
the
master
clock
frequency of
14.31818
MHz,
all of
the
system timing
is derived.
Figure
6 shows
the
breakdown
of
the
master
clock
frequency
to
generate
the timing
signals.
The
video
clock
is exactly
14.31818
MHz/4
and must
be the
most
accurate
frequency
in
the Color
Computer
to provide
a color
picture.
The next
two signals,
E
and
Q,
are used
by
the
CPU
(U1).
These
signals
are
equal
to
the master
clock
divided
by
16;
a frequency
of
0.89
MHz.
The
Q signal leads
the E signal
by
ninety
degrees.
The
E
clock
is
the most
important
timing
signal
to
the CPU
and the
multiplexing
of
RAM
addresses
roughly
follows
this
signal.
RAS*
and
CAS*
are
also triggered
to occur
at
0.89
MHz.
RAS*
strobes
a row
address
into
the
dynamic
RAM,
and
CAS*
strobes
a
column
address
into
RAM.
Figure
6 also shows
the division
of
the RAM between
the
video
address
lines
and the
address lines from
the CPU.
During
any CPU
cycle, the RAM
is
only available
to the CPU
during
the
active
portion of
the
E
clock. However,
this
is sufficient
if
the RAM
is
capable of
completing
a Read
or Write
cycle
during
this time
(the
cycle time is
a simple
matter
of
specifying
the correct
access
time for
the RAM).
The RAM is
available
to the video
display
during
the low portion
of the E
clock
(in
actual fact,
the
display only
requires
the RAM
during
every
other
cycle of
the E
clock). To
make this
VIDEO/CPU
multiplexing
work,
the MC6883
chip
(U10) must keep
the
video
display
address
lines in
sync with
the 6809E
CPU
(U1)
address
lines;
otherwise,
a conflict
could develop
between
the
CPU
and the video
display.
The sync process is
accomplished
immediately
following
reset
by
stopping the video
clock
until
the
VDG
is in
sync with
the CPU.
The
next
major function
of
the MC6883
is address
multiplexing
for
the
dynamic
RAM. First,
the video
address
lines
are reproduced,
using FS*,
HS*, DA0, and
the
VDG
mode
information (FS*
is
detected when
DA0 is in
the
tri-state
mode). These
address lines are
then added
to the
upper address lines from
the
address
offset register
to
form
the
complete
video
address.
The video
address
lines are
then
connected
to
the
multiplexer
bank.
Also connected
to the
multiplexer
bank
is
a 7-bit refresh
counter.
This
7-bit
counter
is
used
during
horizontal
sync
to refresh
the RAM.
At other
times
this
function
is performed
by the video
address
lines.
The
multiplexer
bank first
selects
either
video/refresh
address
lines
or
CPU
address
lines.
Next,
the
multiplexer
selects
between
row
and
column
address
lines.
The multiplexer
then
distinguishes
between
4K,
16K, or
32K dynamic
RAM's
and
presents
the seven
or
eight
address lines
for
the
RAM's
at the
MC6883
output
pins
(pins 28
-
34).
The last
major
function
of
the
MC6883 is
device
selection.
The
sixteen
address
lines
from
the
CPU
are used
to
select
either the
internal
registers
of
the
MC6883
or
up
to eight
external
devices.
This
memory
map
is
shown
in
detail
on
pages
5
through
9. However,
before
the eight
device
selects
leave
the
chip,
they
are
multiplexed
into
three
lines.
At the
output
of
the
MC6883,
a
74LS138
is
used
to
de-multiplex
the
device
selects.
This
74LS138
(U11)
allows
the
Color
Computer
to
select
between
RAM,
three
sources
of
ROM, or
the
two
PIA's.
Also
one
NOR gate
(U29
-
74LS02)
is
used
to
produce
a
clocked
select
signal
for the
ROM's
and the
RAM,
19

Radio Shack Quick Printer II Specifications

General

Brand	Radio Shack
Model	Quick Printer II
Category	Desktop
Language	English