Address
Decoding
This peripheral decodes address
port AFIi
(
175io),
Whenever
this
address is
accessed
by
the
processor via an input instruction the data bus
buffers are enabled.
1 his
mav be
detected
statically
by
disconnecting
the
board
from the TRS-80
computer
and grounding
edge
connector
pins
38(
A6) 3 l( A4)and 19(in).
1C2
pins
1 and 13 should
goto
+
4
volts as
a
result enabling the bus butters with the
4
volt
signal at 1(3 pins
i
,4.
10,
and 13.
Alternative
lv,
the
address logic may be checked dynamically
by entering
a short
assembly
language
routine
with the I Bl (j program This
program does
an input from
Port
AFH and loops
back
and does it overand
overagam.
Positive
pulses should be
seen at 1C2 pins 1
and 13.
and at
IC3 pins
1,4.8,
and
13.
I
:
sing
the
"VI" memor\
till
function
ot I BUG.
choose
a memory
area and enter the following program:
(Address) DB
AF
C3
(Address)
For
example, if
the program
is chosen
to reside at 7000 H. the
steps would
be:
M7000
DB
AF
C3
00
70
To execute
the
program at 7000H,
type J7000,
|jg£|£3£J
Assembly Procedure
Place the board component side
up
into
the bottom half of the
plastic box
so that the three
mounting holes on the board line
up with the shoulders of
the posts in
the box.
Arrange the cable
through two
90 degree bends
and place the existing
cable into
the guide slot
and cable clamp built into the box.
Carefully place the
top of the box
over the bottom
half and,
holding
the
box
securely, turn the box
upsidedownand
replace the
6 screws holding
the box together.
Run the digit test program
(#1)
to verify correct
operation
of the
board.
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