Renesas RL78/G13

RL78/G13 Clock Generator (Clock Switching) CC-RL
R01AN2831EJ0100 Rev. 1.00 Page 41 of 51
May 28, 2015
5.8.17 Getting XT1 Oscillation Clock Status
Figure 5.18 shows the flowchart for getting XT1 oscillation clock status.
Figure 5.18 Getting XT1 Oscillation Clock Status
R_CGC_Get_XT1_Status
YES
NO
Status  Oscillating
f
CLK
status = subsystem
clock?
Status

Not oscillating
return status
f
CLK
= CPU/peripheral hardware clock
Conditions for the subsystem clock status:
CLK.CLS = 1: f
CLK
status is subsystem clock.