8-8
R530/R730
8. Block Diagram and Schematic
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ADDR GROUP
ICH
0
ADDR GROUP
1
CONTROL
2 / 4
DATA GRP 0
DATA GRP 2
DATA GRP 1
DATA GRP 3
C
CPU Socket : 3704-001153
DATE
APPROVAL
THIS DOCUMENT CONTAINS CONFIDENTIAL
A
SAMSUNG ELECTRONICS CO’S PROPERTY.
REV
2
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
OF
DEV. STEP
B
CHECK
SAMSUNG
ELECTRONICS
TITLE
B
A
D
4 3
3
MODULE CODE
PROPRIETARY INFORMATION THAT IS
1
Jun PARK
YM.AHN
HJ.KIM
undefined
9/23/2008
PV
1.0
October 27, 2009 14:27:43 PM
BA41-xxxxxA
8 59
Bremen-L
CPU
PENRYN (1/3)
D:/users/mobile24/mentor/Bremen-L/PV/Bremen-L_MAIN
LAST EDIT
1
SAMSUNG PROPRIETARY
PART NO.
DRAW
C
4
EXCEPT AS AUTHORIZED BY SAMSUNG.
CPU bracket
D
PAGE
2
17
18
12-B1
12-B1
12-B1
12-B1
35
36
12-B1
12-C1
32
33
34
DSTBP3#
AF24
61
62
63
DINV0#
H25
DINV1#
N24
DINV2#
U22
DINV3#
AC20
DSTBN0#
J26
DSTBN1#
L26
DSTBN2#
Y26
DSTBN3#
AE25
DSTBP0#
H26
DSTBP1#
M26
DSTBP2#
AA26
AC25
D58#
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F26
D14#
K22
D15#
H23
D16#
N22
D17#
K25
D18#
P26
A3
STPCLK#
D5
TRDY#
G2
0143854500|bga_479p_sock
CPU1-2
PENRYN
LOCK#
H4
K3
REQ0#
H2
REQ1#
K2
REQ2#
J3
REQ3#
L1
REQ4#
RESET#
C1
RS0#
F3
RS1#
F4
RS2#
G3
SMI#
DEFER#
H5
DRDY#
F21
FERR#
A5
HIT#
G6
HITM#
E4
IERR#
D20
IGNNE#
C4
INIT#
B3
LINT0
C6
LINT1
B4
A6#
K5
A7#
M3
A8#
N2
A9#
J1
ADS#
H1
ADSTB0#
M1
ADSTB1#
V1
BNR#
E2
BPRI#
G5
BR0#
F1
DBSY#
E1
W5
A29#
Y4
A3#
J4
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U2
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V4
A32#
W3
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AA4
A34#
AB2
A35#
AA3
A4#
L5
A5#
L4
A19#
R3
A20#
W6
A20M#
A6
A21#
U4
A22#
Y5
A23#
U1
A24#
R4
A25#
T5
A26#
T3
A27#
W2
A28#
CPU1-1
PENRYN
A10#
N3
A11#
P5
A12#
P2
A13#
L2
A14#
P4
A15#
P1
A16#
R1
A17#
Y2
A18#
U5
34
35
0143854500|bga_479p_sock
12-C1
32
33
12
13
14
12-B4
9
10
11
21
22
7
8
17
18
19
20
12-C1
16
3
4
12-A1
12-A1
31
0
12-B1
12-A1
3
2
1
4
7
8
4
12-B1
3
12-D4
27
28
12-D4
45
46
47
R571
56
12-B1
12-B1
P1.05V
15
12-D4
12-D4
12-B1
41
42
43
44
38
39
40
28
25
23
37
1
2
27
53
5424
26
58
57
49
50
1
MNT1
MNT2
2
3
MNT3
MNT4
4
10
59
60
M501
BA75-01937A
SUPLECODE
6
55
56
9
29-B1
5
29-C1
29-C1
29-B1
52
0
29-B1
29-C1
29-C1
31
12-D1
51
12-B1
48
11
29
30
12-B1
12-B1
21
22
12
12-B1
19
20
29-C1
12-C1
12-C1
12-B1
12-B1
12-B1
12-B1
5
6
29
30
24
25
26
12-C1
12-C1
23
15
16
12-D1
12-B1
CPU1_ADS#
CPU1_IERR#_MN
CPU1_CPURST#
CPU1_INTR
13
14
CPU1_D#(63:48)
CPU1_D#(47:32)
CPU1_DBI0#
CPU1_ADSTB0#
CPU1_ADSTB1#
CPU1_D#(31:16)
CPU1_D#(15:0)
CPU1_REQ#(4:0)
CPU1_A#(16:3)
CPU1_DSTBN2#
CPU1_DSTBN3#
CPU1_DSTBP2#
CPU1_DSTBP3#
CPU1_DSTBP1#
CPU1_DSTBN1#
CPU1_DSTBP0#
CPU1_DBI1#
CPU1_DSTBN0#
CPU1_A#(35:17)
CPU1_DBI2#
CPU1_DBI3#
CPU1_INIT#
CPU1_NMI
CPU1_LOCK#
CPU1_RS0#
CPU1_RS1#
CPU1_RS2#
CPU1_SMI#
CPU1_STPCLK#
CPU1_TRDY#
CPU1_A20M#
CPU1_BNR#
CPU1_BPRI#
CPU1_BREQ#
CPU1_DBSY#
CPU1_DEFER#
CPU1_DRDY#
CPU1_FERR#
CPU1_HIT#
CPU1_HITM#
CPU1_IGNNE#
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