8-9
R530/R730
8. Block Diagram and Schematic
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- This Document can not be used without Samsung's authorization -
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RSVD
THERMAL
H CLK
XDP/ITP SIGNALS
0
0
1
1
0
0
0
0.7125 V
1
1
0
1
0 1
APPROVAL
0
0
1
1
0
0
1
1
REV
0
near the CPU
1
0
Active
1
A
2
SAMSUNG ELECTRONICS CO’S PROPERTY.
0
0
1.4625 V
1
1
0
0
0
0
0
CPU Socket : 3704-001153
0.9125 V
1
0
BSEL0, BSEL2
BSEL0, BSEL1, BSEL2
1
1
FRQ
0
0
1.2250 V
0.0000 V
1
1
200M
1
0
0
0.5500 V
0
0
0
1
MODULE CODE
2
1
BSEL
1
1.3125 V
0
1
1
0
Minimize coupling of any switching signals to this net.
1
1
0
0
1
0
1
1
1
1
1
0
0
0
0
0
0
1
1
0
0
0
1
1.3000 V
0.3500 V
0
0
0
0
1
1
0
1
1
1
1
1
0
*"1111111" : 0V power good asserted.
1
1
1
1
1
0
0
0
1
1.1750 V
0
0
0
1
0
1
1
0.0000 V
0
1
0
0
0
1.1375 V
0
0
*Yonah Processor (2.33 GHz / 800 MHz : TBD)
0
0
0
FSB
Route the VCC/VSSsense as a Zo=55ohm traces with equal length.
0
1
1
0
0
0
FSA
0
1
1
0
0.3750 V
Pull-down
1
DATE
0
0
0
DEV. STEP
1
0
0.6000 V
0.0625 V
1
1
1
0
1
0
0
0
1
OF
1
0
0
166M
0
1
0
1
1
0
1
1
0
1
1
0
0
0
1
1.0625 V
0
1
0.3375 V
0.1500 V
0
0
0.8125 V
1
FSC
1.5000 V
1
0
1
1
0
0
0.4875 V
1
1
1
0.5375 V
0
0.2375 V
1
1
0
1.4875 V
0
1
0
0
0
0
0
1
0
1
0.7250 V
0
SI team request
0.2250 V
1
1
1
0
266M
0.0375 V
1
0
1
0.1625 V
1
1
0
1
0
0.0875 V
1
0
1
0
1
0
0
1
0
0
0
1
1
1
1
1
0
0
Observe 3:1 spacing b/w VCC/VSSsense lines and 25mil away
1
FSB 800 MHz
1
1
0
DPRSLPVR
0
0
1
1
1
0
1.2625 V
1.3625 V
0.3125 V
0
0
0
0
0.4750 V
1
0
0
DPRSTP*
1
0
0
1
0
1
1
1
1
1
1
0
0.5000 V
0
0
0
1
1
0
1
0
0
1
1
1
0.4625 V
1
SAMSUNG
0
0
0
1
0
3
0
-> delete and change layout (ECAE)
0
0
1
1
1
1
1
1
1
1
1
1
0
1
1
0
TITLE
1
1
0
1
1
1
0
1
1
0
1
0
1
1
0
(preferred 50mil) from any other signal. And GND via 100mil away
0.2625 V
1
1
0
1
0
1
1
0
1
0
1
0
PSI2*
1
0
1
1
0
1
1.1125 V
1
0
1
1
1
1
1
0
1
0
0
1
0
0.6375 V
0.2875 V
0
1
0.5250 V
1
1
0
0
1
4
0
1
1
0
0
1
0
IMVP-6
0
0
0.3000 V
1
0.7875 V
1
1
0
1
FSB 1067 MHz
1
0
0
1
1
0.8500 V
0
0
1.1875 V
1
1
0.6875 V
0 or 1
0
1
1.4750 V
1
1
0
1.4000 V
0.0500 V
10
0.5875 V
1
1
0
1
0.0750 V
0
0
0.5125 V
0
0
1
0
1
1
0
0
Dual Mode Region
1
1
1
0
0
0.4000 V
1
1
0
0.5750 V
1
1
0
0
1
0
0.4375 V
0
1
0
1
1
0
DRAW
0
0
1
1
1.0375 V
1
0
0
1
0
0
0
0
1
1
1
1
1
1
0
0.3625 V
1
1
1
1
1.4500 V
1
0
0
1
0
1
0
1
0
1
1
0
0
1
0
1
C
0
1
0
1
of the first GTLREF0 pin with Zo=55ohm trace.
1
0
0
EXCEPT AS AUTHORIZED BY SAMSUNG.
V
05
23.
01
0
0
0
0
0
0
0
0.2500 V
0
0
1
0
1
0
0.7000 V
0.0250 V
0
Deeper Sleep/Extended Deeper Sleep
1
1
0
1.2750 V
1
0.9375 V
1
1
0
1.2875 V
0
1
0
0
0
1
1
1
0
0
1
0
0
0
1
0
0
1
0
1
0.1375 V
1
0.0000 V
1 1
0.0000 V
1
0
0
1
1
1
0.5625 V
VID(6:0)
0
1
1
0
1
1
1
1
1
1
0
1
0
1.0750 V
0
0
0
1
0.0125 V
1
1
0
0.1125 V
0
0
0.3875 V
1.3875 V
1
0
0.0000 V
0.0000 V
trace shorter than 1/2" to their respective Banias socket pins.
1
1
1
1
0
0
1
0
Voltage
0.8250 V
0
1
1
0
1
0
1.0875 V
0
0
1
0
1
0
0
1
0
1
0
0
3
1
0
0
0
1
0
0
0.4250 V
0
1
1
0
0
1
0
1
0
0
0
1
0
Deeper Slp
0
0
1
1
1
0
0
1
1
Voltage
0
0
1
1
0
0
1
1
1
1
0.6500 V
1
0.8375 V
0
D
0.6250 V
1
0
0
Active Mode
0
1
0
C
PAGE
1.4375 V
0
0
1 1
0
1
1
1
1.3750 V
1.0000 V
1
0
1
1
1
1
1
0
0.2750 V
1
0
PSI2*
1
1
1
1.0500 V
1.4125 V
1
1
GTLREF : Keep the Voltage divider within 0.5"
0
0
0
1
0
1
0
SAMSUNG PROPRIETARY
0
1
0
1
1
0
0
0.8000 V
0
0.7750 V
0
0
1
1
0.7375 V
00
1
1
0
1
1
Active/Deeper Sleep
1
1
1.1250 V
PART NO.
0
0
0
0
1
1
0
1
1
1
0
COMP0,2(COMP1,3) should be connected with Zo=27.4ohm(55ohm)
1
1
1
1
0.4500 V
0
0
1.3250 V
0
0
0.7625 V
0
0
0
1
1
0
1
1
0
0
1
1
0.0000 V
0
0
0
0
0
0
0
1
0
1
B
1
1
0
0.6750 V
0
0
1
1.1500 V
1
1
1
1
1.0125 V
1
0
1
0
from each of the VCC/VSS test point vias.
1
1
1
0.8625 V
0
0
DPRSTP*
1
1
1
1
0
0
0
0
1
CHECK
1.2375 V
1
1
1
1
LAST EDIT
0
1
0
0
0.9875 V
0
1.2500 V
0
0
1
0.4125 V
1
0
0
0
1
1
1
0
1
1
0
1
1
0
1.2125 V
0
1
1
0
0
0
1
0
0
1
1.1000 V
1
1
1
0
1
0
ELECTRONICS
0
0
1
1
0.2125 V
0.6125 V
1
0
0
0
1
1
1
0
0
0
0
0
1
0
0.9625 V
0
1
1
1
1
1
1
1
1
0
1
VID(6:0)
1.4250 V
1.1625 V
1
0
1
1.3500 V
0.1000 V
0
0
A
D
0
0
1
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
0
0
0
0
1
0
0
1
0.0000 V
CPU Core Voltage Table
0
1
1
1
0
0
0
1
0
0
1
0
DPRSLPVR
0
1
1
1
1.0250 V
0
1
0.7500 V
1
0
1
1
1
1
1
1
0
0
0
1
1 1
0
1
0
0
1
0.8875 V
0
1
0
1
4
1
0
1
0
0
1
1
0
0
0.1750 V
1
0
0
0
0
0
0
THIS DOCUMENT CONTAINS CONFIDENTIAL
0
1.2000 V
1
0
VID(6:0)
0
0
0
1
1
0
1
1
0.8750 V
0
1
0
0
1
0
0.1250 V
0
0
1
1
0
1
1
1
0
0
0.2000 V
1
1
1
0 or 1
1
1
0
1
0
1
1
0
1
0
1
0.9500 V
1
1
PROPRIETARY INFORMATION THAT IS
1
0.9250 V
1
0
0
1
0
1
1
1
0
1
1.3375 V
1
0
0
Dual Mode Region
0.9750 V
1
0
0
0
0.1875 V
1
GND test points within 100mil of the VCC/VSSsense at the end of the line.
1
0
0
0
1
1
0.9000 V
1
0
1
0
Voltage
0
1
0
0
0.6625 V
Jun PARK
YM.AHN
HJ.KIM
undefined
9/23/2008
PV
1.0
October 27, 2009 14:27:43 PM
BA41-xxxxxA
9 59
Bremen-L
CPU
PENRYN (2/3)
D:/users/mobile24/mentor/Bremen-L/PV/Bremen-L_MAIN
1
54.9
1%
2
100nF
C567
10V
R526
R518
54.9
1%
C580
10000nF-X5R
6.3V
5
25V
C582
10nF
100nF
C569
10V
27.4
54-D4
10-C4,54-A4
R531
1%
10V
C563
100nF
R553
1%
54.9
100nF
10V
nostuff
54-C413-B1,29-C1
nostuff
10V
C571
P1.05V
0
C531
100nF
27.4
1%
R555
31-D3
11-C4,12-A3
P1.05V
11-C4,12-A3
10V
C560
100nF
1%
R519
1K
9-A4
11-C1
11-C4,12-A3
11-C1
1
9-C3
3
9-C3
C557
10V
4
10-B4,54-A4
12-B1
nostuff
100nF
29-C1
56
R572
7-C2
1%
R517
2K
AF5
VID_2
AE5
VID_3
AF4
VID_4
AE3
VID_5
AF3
VID_6
AE2
AE7
VSSSENSE
J6
VCCP_2
M6
VCCP_3
N6
VCCP_4
T6
VCCP_5
R6
VCCP_6
K21
VCCP_7
J21
VCCP_8
M21
VCCP_9
AF7
VCCSENSE
VID_0
AD6
VID_1
TRST#
B26
VCCA_1
C26
VCCA_2
K6
VCCP_1
N21
VCCP_10
T21
VCCP_11
R21
VCCP_12
V21
VCCP_13
W21
VCCP_14
V6
VCCP_15
G21
VCCP_16
D25
C24
TEST3
AF26
TEST4
AF1
TEST5
A26
TEST6
C3
TEST7
C7
THERMTRIP#
THRMDA
A24
THRMDC
B25
AB5
TMS
AB6
RSVD_6
D2
RSVD_7
D22
RSVD_8
D3
RSVD_9
F6
D7
SLP#
AC5
TCK
AA6
TDI
AB3
TDO
C23
TEST1
TEST2
GTLREF
PRDY#
AC2
PREQ#
AC1
D21
PROCHOT#
AE6
PSI#
D6
PWRGOOD
RSVD_1
M4
RSVD_2
N5
RSVD_3
T2
RSVD_4
V3
RSVD_5
B2
C21
R26
COMP0
U26
COMP1
COMP2
AA1
Y1
COMP3
DBR#
C20
E5
DPRSTP#
B5
DPSLP#
D24
DPWR#
AD26
BCLK0
A22
BCLK1
A21
BPM0#
AD4
BPM1#
AD3
BPM2#
AD1
BPM3#
AC4
BSEL0
B22
BSEL1
B23
BSEL2
9-C3
0143854500|bga_479p_sock
CPU1-3
PENRYN
1%
29-C1
R524
54.9
EC502
220uF
2.5V
9-A4
P1.5V
9-C3
nostuff
12-B4
7-C2
9-A4
1%
R538
54.9
R521
54.9
1%
6
P1.05V
P1.05V
9-A4
CPU1_GTLREF_MN
CPU1_TRST#
CPU1_THRMTRIP#
13-B1,29-B1
54-C4
CPU1_DPWR#
CPU1_PSI#
CPU1_BSEL0
CPU1_BSEL1
CPU1_BSEL2
CPU1_VCCSENSE
CPU1_TCK
CPU1_TDI
CPU1_TMS
ITP3_DBRESET#
CPU1_PROCHOT#_MN
CPU1_COMP3_MN
CPU1_COMP1_MN
CPU1_COMP2_MN
CPU1_COMP0_MN
CPU1_TCK
CPU1_TDI
CPU1_TMS
CPU1_TRST#
CPU1_VID(6:0)
CLK0_HCLK0
CLK0_HCLK0#
CPU1_PWRGDCPU
CPU1_DPSLP#
CPU1_SLP#
CPU1_VSSSENSE
CPU1_DPRSTP#
CPU2_THERMDA
CPU2_THERMDC
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