8-11
R530/R730
8. Block Diagram and Schematic
- 이 문서는 삼성전자의 기술 자산으로 승인자만이 사용할 수 있습니다 -
- This Document can not be used without Samsung's authorization -
Samsung
Confidential
Samsung
Confidential
Samsung
Confidential
IDT : 1205-003159
SAMSUNG
VDD_SRC_IO
BSEL1
A
C
SRC2
DATE
400 MHz
EXCEPT AS AUTHORIZED BY SAMSUNG.
SRC4
0
2
SATA
CLK REQ E
333 MHz
0
0
SRC6
Pin 24/25
APPROVAL
LAST EDIT
CK505M
0
4
VDD_48
3
->delete and change layout? (ECAE)
D
THIS DOCUMENT CONTAINS CONFIDENTIAL
HIGH
0
DOT_96/DOT_96#
VDD_PLL3_IO VDD_IO
133 MHz
100 MHz1
BSEL0
1
VDD_CPU_IO
SEL_LCDCLK*
D
27M & 27M_SS
DEV. STEP
1
VDD_PCI
CHECK
PROPRIETARY INFORMATION THAT IS
Place 14.318MHz within
1
B
CLK REQ F
00
GMCH
CLK REQ A
OF
RSVD
1
HOST CLK
PAGE
DEVICE
200 MHz
Pin 20/21
266 MHz
FSC
CLK REQ
2
ELECTRONICS
VDD_REF
PART NO.
SL : 1205-003533
PEG_CLK/PEG_CLK#
SAMSUNG ELECTRONICS CO’S PROPERTY.
3
FSB
4700nF->10uF (Y5V->X5R)
FSA
EXP3_CLKREQ#
1
VDD_SRC
500mils of CK-505
BSEL2
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
0
C
B
SRC PORT
1
1
This part is 64pin QFN package.
1
VDD_PLL3
CLK REQ B
0
166 MHz
REV
SRC8
SAMSUNG PROPRIETARY
4
SRC_0/SRC_0#
MODULE CODE
0
0 0
MINI CARD
1
A
TITLE
Jun PARK
YM.AHN
HJ.KIM
undefined
9/23/2008
PV
1.0
October 27, 2009 14:27:43 PM
BA41-xxxxxA
11 59
Bremen-L
MAIN_CLOCK_CIRCUIT
D:/users/mobile24/mentor/Bremen-L/PV/Bremen-L_MAIN
CK_Clock_505M
1
DRAW
VDD_CPU
LOW
1
1
1
2.2K
R100
10V
40-C4
P1.5V
C847
100nF
29-B1
31-B3
33
R107
1%
475
R690
1%
C869
31-B3
50V
C123
0.018nF
6.3V
10000nF-X5R
BLM18PG181SN1
B521
40-C4
9-C4,12-A3
C851
10000nF-X5R
6.3V
2801-004874
1
2
nostuff
31-B417-B4,18-B4
Y2
14.31818MHz
1%
R684
10K
29-B1
13-B1
12-B1
R691
22
6.3V
BLM18PG181SN1
B522
31-C1
nostuff
C844
10000nF-X5R
41-C3
31-C1
0.033nF
50V
C823
nostuff
1%33
R689
R108
22
R702
10K
1%
31-C3
10V
100nF
C849
22
R692
19-C4
40-C4
34-A4
475
R701
1%
R103
42-C3
10V
100nF
C152
33
1%
6.3V
C834
10000nF-X5R
31-B417-B4,18-B4
nostuff
50V
C134
0.022nF
12-B1
P3.3V
R693
22
50V
C122
0.018nF
1%
R699
10K
10000nF-X5R
C877
100nF
nostuff
6.3V
10V
C838
10V
100nF
C837
30-C2
C865
100nF
10V
44-B4
31-C3
19-C4
6.3V
10000nF-X5R
C843
42-C3
13-A1
10K
R703
nostuff
1%
C822
50V
0.033nF
nostuff
9-D4
31-A3
9-C4,12-A3
nostuff
31-A3
22
R110
C821
50V
0.033nF
42-C3
9-D4
13-B1
100nF
C872
10V
VSS_CPU
22
VSS_IO
15
VSS_PCI
26
VSS_PLL3
1
VSS_REF
30
VSS_SRC1
VSS_SRC2
36
49
VSS_SRC3
3
XTAL_IN
XTAL_OUT
2
19
VDD_IO
9
VDD_PCI
23
VDD_PLL3
VDD_PLL3_IO
27
4
VDD_REF
46
VDD_SRC
33
VDD_SRC_IO1
43
VDD_SRC_IO2
52
VDD_SRC_IO3
VSS_48
18
59
SRC7#_CLKREQE#
51
SRC7_CLKREQF#
53
SRC8#_ITP#
54
SRC8_ITP
37
SRC9
SRC9#
38
THERM_GND
65
17
USB_FS_A
16
VDD_48
62
VDD_CPU
56
VDD_CPU_IO
39
SRC11#_CLKREQG#
40
SRC11_CLKREQH#
28
SRC2
29
SRC2#
32
SRC3#_CLKREQD#
31
SRC3_CLKREQC#
SRC4
34
SRC4#
35
48
SRC6
47
SRC6#
50
10
PCI_1_CLKREQ_B#
11
PCI_2
12
PCI_3
13
PCI_4_SEL_LCDCLK#
5
REF_FS_C_TEST_SEL
7
SCL
6
SDA
21
SRC0#_DOT96#
20
SRC0_DOT96
41
SRC10
42
SRC10#
CPU0#
58
CPU1_MCH
57
CPU1_MCH#
44
CPUSTOP#
64
FSB_TESTMODE
25
LCDCLK#_27M_SS
24
LCDCLK_27M
NC
55
14
PCIF_5_ITP_EN
45
PCISTOP#
8
PCI_0_CLKREQ_A#
U9
1205-003156
SLG8SP513
63
CLKPWRGD_PWRDN#
61
CPU0
60
P3.3V
19-B2
10K
R683
1%
CLK3_DBGLPC_R_MN
19-B2
9-C4,12-A3
nostuff
CLK3_PCLKICH_R_MN
CLK3_PCLKMICOM_R_MN
CLK3_ICH14_R_MN
CLK3_USB48_R_MN
CLK1_27M
CLK1_27M_SS
CLK3_VDD_SRC_IO_MN
CLK3_VDD_REF_MN
CLK1_PEG
CLK1_PEG#
CLK1_MINIPCIE#
CLK1_27M_R_MN
CLK1_27M_SS_R_MN
MCH3_CLKREQ#_R_MN
CHP3_SATACLKREQ#_R_MN
CLK1_MCH3GPLL
CHP3_SATACLKREQ#
CLK3_PCLKMICOM
MCH3_CLKREQ#
CLK3_DBGLPC
MIN3_CLKREQ#
CLK1_PCIEICH
CLK1_PCIELOM
LAN3_CLKREQ#
CLK0_HCLK0
CLK3_USB48
SMB3_CLK
SMB3_DATA
CHP3_CPUSTP#
CHP3_PCISTP#
CPU1_BSEL2
CPU1_BSEL0
CLK3_ICH14
CLK3_PCLKICH
CLK3_MMC48
CLK1_PCIEICH#
CLK1_PCIELOM#
CLK1_MINIPCIE
CLK1_MCH3GPLL#
CLK_XTAL_IN_MN
CLK_XTAL_OUT_MN
CLK1_SATA
CLK1_SATA#
CLK3_PWRGD
CPU1_BSEL1
CLK0_HCLK1#
CLK0_HCLK1
CLK0_HCLK0#
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