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Samsung R528 - Page 123

Samsung R528
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8-12
R530/R730
8. Block Diagram and Schematic
- 이 문서는 삼성전자의 기술 자산으로 승인자만이 사용할 수 있습니다 -
- This Document can not be used without Samsung's authorization -
Samsung
Confidential
Samsung
Confidential
Samsung
Confidential
1 OF 5
VTT
HOST DATA BUS
VTTLF
NC
HOST CONTROL
HOST ADDRESS BUS
VCC CORE
CFG
CFG(5)
APPROVAL
DMI Lane Reversal
Low
Simultaneously
MODULE CODE
PROPRIETARY INFORMATION THAT IS
CFG(7)
A
*POCAFEB-12 Only (Remove in MP Model)
Enabled (def.)
CHECK
CFG(19)
DRAW
2
PCIE Loop Back Enable
PART NO.
CFG(6)
C
CFG#
PCIE Loop Back Disable(def)
iTPM option
1
ELECTRONICS
DMIx2
REV
Only(def.)
DATE
SDVO or PCIE X1
(def. : default Option)
CFG(9)
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
3
SDVO and PCIE X1
Current Setting
ME Crypto confidentiality (def.)
PAGE
Dynamic ODT
SAMSUNG
DEV. STEP
THIS DOCUMENT CONTAINS CONFIDENTIAL
4
2
CFG(20)
D
1608
TITLE
D
4
B
CFG(16)
C
OF
iTPM Host Interface Enable
CFG(10)
High
Normal
Jun PARK
YM.AHN
HJ.KIM
undefined
9/23/2008
PV
1.0
October 27, 2009 14:27:43 PM
BA41-xxxxxA
12 59
Bremen-L
MCH_CANTIGA_GM_DDR2
CANTIGA (1/5)
D:/users/mobile24/mentor/Bremen-L/PV/Bremen-L_MAIN
B
ME Crypto no confidentiality
3
PEG Reversal (def.)
LAST EDIT
SAMSUNG PROPRIETARY
DMI Lane Normal (def.)
iTPM Host Interface Disable (def.)
1
Dynamic ODT Disabled
DMIx4 (def.)
SAMSUNG ELECTRONICS CO’S PROPERTY.
EXCEPT AS AUTHORIZED BY SAMSUNG.
A
24
35
45
39
40
0
20
25
12-C4
53
6.3V
C766
10000nF-X5R
8-B3
30
41
10V
100nF
C759
16
19
9-C4,11-C4
4
10
8-C4
19
9
9
12
17
30
57
50
8
8-C1
20
8-C1
22
10V
C635
100nF
8-C1
23
56
8-C3
32
8-C3
49
11-C1
52
8-C3
221
R580
23
36
12-A4
1%
8-C4
8-B1
C92
470nF
16V
14
C646
470nF
16V
P1.05V
5
7
28
8-C3
1
100nF
C740
10V
8-C3
37
16
T2
VTT_6
T5
VTT_7
T6
VTT_8
T7
VTT_9
T8
21
8-C3
VTT_19
U6
VTT_2
T11
VTT_20
U7
VTT_21
U8
VTT_22
U9
V1
VTT_23
V2
VTT_24
V3
VTT_25
VTT_3
T12
VTT_4
T13
VTT_5
VTTLF_3
L1
VTT_1
T10
VTT_10
T9
VTT_11
U1
VTT_12
U10
VTT_13
U11
VTT_14
U12
VTT_15
U13
VTT_16
U2
VTT_17
U3
VTT_18
U5
VCC_NCTF_41
Y29
VCC_NCTF_42
Y30
VCC_NCTF_43
Y32
VCC_NCTF_44
AC29
VCC_NCTF_5
AC30
VCC_NCTF_6
AC32
VCC_NCTF_7
AE29
VCC_NCTF_8
AE30
VCC_NCTF_9
VTTLF_1
A8
VTTLF_2
AB2
AL32
VCC_NCTF_32
AM30
VCC_NCTF_33
AM32
VCC_NCTF_34
U30
VCC_NCTF_35
U32
VCC_NCTF_36
V29
VCC_NCTF_37
V30
VCC_NCTF_38
W29
VCC_NCTF_39
AB30
VCC_NCTF_4
W30
VCC_NCTF_40
W32
VCC_NCTF_22
AK26
VCC_NCTF_23
AK28
VCC_NCTF_24
AK29
VCC_NCTF_25
AK30
VCC_NCTF_26
AK32
VCC_NCTF_27
AL26
VCC_NCTF_28
AL28
VCC_NCTF_29
AA32
VCC_NCTF_3
AL29
VCC_NCTF_30
AL30
VCC_NCTF_31
VCC_NCTF_12
AG30
VCC_NCTF_13
AG32
VCC_NCTF_14
AH29
VCC_NCTF_15
AH30
VCC_NCTF_16
AH32
VCC_NCTF_17
AJ29
VCC_NCTF_18
AJ32
VCC_NCTF_19
AA30
VCC_NCTF_2
AK23
VCC_NCTF_20
AK24
VCC_NCTF_21
AK25
Y34
VCC_35
VCC_4
AB34
VCC_5
AC26
VCC_6
AC28
VCC_7
AC33
VCC_8
AC34
VCC_9
AE26
AA29
VCC_NCTF_1
AE32
VCC_NCTF_10
AF30
VCC_NCTF_11
AG29
VCC_25
AK33
VCC_26
AM33
VCC_27
T32
VCC_28
U33
VCC_29
VCC_3
AA34
U34
VCC_30
V33
VCC_31
V34
VCC_32
W33
VCC_33
Y33
VCC_34
VCC_15
AG25
VCC_16
AG26
VCC_17
AG33
VCC_18
AG34
VCC_19
VCC_2
AA33
AH23
VCC_20
AH25
VCC_21
AH28
VCC_22
AJ23
VCC_23
AJ26
VCC_24
AJ33
F12
H_RS#_1
C8
H_RS#_2
H_SWING
C5
C9
H_TRDY#
VCC_1
AA28
VCC_10
AE33
VCC_11
AF23
VCC_12
AF25
VCC_13
AF28
AF33
VCC_14
AG24
H_DVREF
B11
H9
H_HIT#
E12
H_HITM#
H11
H_LOCK#
H_RCOMP
E3
B15
H_REQ#_0
K13
H_REQ#_1
F13
H_REQ#_2
B13
H_REQ#_3
B14
H_REQ#_4
B6
H_RS#_0
H_DINV#_3
J11
H_DPWR#
F9
H_DRDY#
L10
H_DSTBN#_0
M7
H_DSTBN#_1
AA5
H_DSTBN#_2
AE6
H_DSTBN#_3
L9
H_DSTBP#_0
M8
H_DSTBP#_1
AA6
H_DSTBP#_2
AE5
H_DSTBP#_3
AG2
H_D#_62
AD6
H_D#_63
F6
H_D#_7
D4
H_D#_8
H3
H_D#_9
B10
H_DBSY#
E9
H_DEFER#
J8
H_DINV#_0
L3
H_DINV#_1
Y13
H_DINV#_2
Y1
H_D#_52
AD3
H_D#_53
AD7
H_D#_54
AE14
H_D#_55
AF3
H_D#_56
AC1
H_D#_57
AE3
H_D#_58
AC3
H_D#_59
H2
H_D#_6
AE11
H_D#_60
AE8
H_D#_61
H_D#_42
AA9
H_D#_43
AA11
H_D#_44
AD11
H_D#_45
AD10
H_D#_46
AD13
H_D#_47
AE12
H_D#_48
AE9
H_D#_49
H6
H_D#_5
AA2
H_D#_50
AD8
H_D#_51
AA3
AD14
H_D#_33
Y6
H_D#_34
Y10
H_D#_35
Y12
H_D#_36
Y14
H_D#_37
Y7
H_D#_38
W2
H_D#_39
G2
H_D#_4
AA8
H_D#_40
Y9
H_D#_41
AA13
H_D#_23
R1
H_D#_24
N5
H_D#_25
N6
H_D#_26
P13
H_D#_27
N8
H_D#_28
L7
H_D#_29
E6
H_D#_3
N10
H_D#_30
M3
H_D#_31
Y3
H_D#_32
H_D#_13
N12
H_D#_14
J6
H_D#_15
P2
H_D#_16
L2
H_D#_17
R2
H_D#_18
N9
H_D#_19
F8
H_D#_2
L6
H_D#_20
M5
H_D#_21
J3
H_D#_22
N2
A9
H_BNR#
F11
H_BPRI#
G12
H_BREQ#
C12
H_CPURST#
E11
H_CPUSLP#
F2
H_D#_0
G8
H_D#_1
M9
H_D#_10
M11
H_D#_11
J1
H_D#_12
J2
H_A#_35
C15
H_A#_4
F16
H_A#_5
H13
H_A#_6
C18
H_A#_7
M16
H_A#_8
J13
H_A#_9
H12
H_ADS#
B16
H_ADSTB#_0
G17
H_ADSTB#_1
H_AVREF
A11
H_A#_25
L16
H_A#_26
C21
H_A#_27
J17
H_A#_28
H20
H_A#_29
A14
H_A#_3
B18
H_A#_30
K17
H_A#_31
B20
H_A#_32
F21
H_A#_33
K21
H_A#_34
L20
P17
H_A#_15
F17
H_A#_16
G20
H_A#_17
B19
H_A#_18
J16
H_A#_19
E20
H_A#_20
H16
H_A#_21
J20
H_A#_22
L17
H_A#_23
A17
H_A#_24
B17
CFG_6
M24
CFG_7
E21
CFG_8
C23
CFG_9
HPLL_CLK
AH7
AH6
HPLL_CLK#
P16
H_A#_10
R16
H_A#_11
N17
H_A#_12
M13
H_A#_13
E17
H_A#_14
CFG_14
M20
CFG_15
L21
CFG_16
H21
CFG_17
P29
CFG_18
R28
CFG_19
P25
CFG_2
T28
CFG_20
P20
CFG_3
P24
CFG_4
C25
CFG_5
N24
0904-002376
T25
CFG_0
R25
CFG_1
C24
CFG_10
N21
CFG_11
P21
CFG_12
T21
CFG_13
R20
8-B2
U7-1
EB88CTPM
8-C3
5
6
8-C2
8-C3
P1.05V
8-C3
58
1%
100
R585
12-B4
33
8-B1
26
8-C3
4
26
10V
13
8-C3
0
C818
100nF
31
51
14
7
3
46
9-C4,11-C4
8-C2
8-C2
48
32
12
11
27
2
11-B1
28
34
15
P1.05V
18
9-D4
nostuff
34
29
10000nF-X5R
C809
6.3V
59
1000nF-X5R
C794
6.3V
54
8-C3
P1.05V
60
55
62
12-B4
42
P1.05V
38
25
3
21
35
8-B1
4
24.9
R67
6
63
1%
18
31
8-B2
8-C1
2
8-B4
29
9-D4
nostuff
9-C4,11-C4
1
EC504
220uF
2.5V
AD
3
22
8-B2
6.3V
10000nF-X5R
C724
R633
2.2K
15
27
8-C3
nostuff
1%
8
nostuff
33
1K
R592
11
AD
2.5V
220uF
EC503
470nF
C778
10
17
16V
44
47
8-C3
R588
2K
1%
43
13
8-C3
MCH1_H_RCOMP_MN
MCH1_VTTLF2_MN
MCH1_CFG6_MN
61
24
CPU1_LOCK#
CPU1_RS0#
CPU1_RS1#
CPU1_RS2#
CPU1_TRDY#
CPU1_REQ#(4:0)
CPU1_DPWR#
MCH1_HVREF
MCH1_VTTLF1_MN
MCH1_VTTLF3_MN
MCH1_HXSWING
MCH1_HVREF
CPU1_BSEL0
CPU1_BSEL1
CPU1_BSEL2
CPU1_D#(63:0)
CPU1_A#(35:3)
CPU1_ADS#
CPU1_ADSTB0#
CPU1_ADSTB1#
CPU1_BNR#
CPU1_BPRI#
CPU1_BREQ#
CPU1_SLP#
CPU1_CPURST#
CLK0_HCLK1#
CLK0_HCLK1
CPU1_DBSY#
CPU1_DEFER#
CPU1_DBI0#
MCH1_HXSWING
CPU1_DBI1#
CPU1_DBI2#
CPU1_DBI3#
CPU1_DRDY#
CPU1_DSTBN0#
CPU1_DSTBN1#
CPU1_DSTBN2#
CPU1_DSTBN3#
CPU1_DSTBP0#
CPU1_DSTBP1#
CPU1_DSTBP2#
CPU1_DSTBP3#
CPU1_HIT#
CPU1_HITM#

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