Sanyo DC D30 - Page 21

IC BLOCK DIAGRAM (CD)
1€104 LC7866E (Digital Signal Processor )
PIN
I 1 | TEST1 la | For TEST. Normal time is non connection.
AO
iL
2
3 Al
4 PDO
ee ae a ae en
EFMO. This signal use SLICE LEVEL CONTROL.
Positive output through amplitude limiter. Antiphase of EFMO.
This signal use SLICE LEVEL CONTROL.
Fa | ccm | | Inputting HF signal of 1~2Vp.p. This signal use SLICE LEVEL
CONTROL.
[a | rest2 | 1 [ For Test. Normal time is non connection. |
| 10 | civ+ | 0 | output for DISC MOTOR CONTROL.
111 | cuv- | 0 | output for DISC MOTOR CONTROL.
CLV rough Servo time : Output “H”
12 ViP
Input from VCO output in LA9210 .(8.6436MHz)
Phase comparison output of VCO and EFM signal.
Phase control time : Output”L”
13 Focs Output “H” : Lens pull up with slowly than stop the Focus
14 FST Servo. If FZD generate, it reset output of FOCS. For lead-in of
15 FZD Focus
Comply with command of track jump, it oscillate kick Pulse,
JP* & JP". It jump the prescribed number of track (1,4,16,64).
foe] nn
ts oe Comply with command of track jump, it oscillate kick Pulse,
JP* & JP’. It jump the prescribed number of track (1,4,16,64).
| 18 | pcx | 0 | PCK Monitor (4.3218MHz)
a ESEQ Fo | SYNC (FS of truth) detected from EFM signal = SYNC of
counter : “H” (Latch Output during in 1 frame)
TOFF
TGL
THLD
[23 fe sesrae | |
[24 | voo [|
lz) ® [|
26 JP*
| 27 | oemo |_|
| 2a | testa | |
Lo _|
Lt
Comply with command of track jump, it oscillate kick Pulse,
JP* & JP*. It jump the prescribed number of track (1,4,16,64).
For TEST. Normal time is non connection.
+5V
Comply with command of track jump, it oscillate kick Pulse,
JP* & JP”. It jump the prescribed number of track (1,4,16,64).
For adjustment of production process. Sound on function.
For TEST. Normal time is non connection.
Output is “H” time, it need de-emphasis
H
For TEST. Normal time is ”
Pee eee
SLICE LEVEL vco CLOCK
CONTROL OSCILLATION
CLOCK CONTROL
SYNCHRONIZATION
DETECTION
EFM DEMODULAT ION
C1 C2 ERROR DETECTION
& CORRECTION FLAG
PROCESSING
SUBCODE
SEPARATION
Bs Q CRC
© uCOM
XTAL-SYSTEM
TIMING
GENARATOR
PIN
NAME 140 DESCRIPTION
SMP2 Output of signal to DAC, Signal of Latch & L/R select, Signal
SMP1 for Sampling Hold
LRCLK
SMP.
DFOUT
DACLK
P
x
Output of signal to DAC, Signal of Latch & L/R select, Signal
w ww
b None
for Sampling Hold
Ou
for
Output of signal to DAC, Signal of Latch & L/R select, Signal
for Sampling Hold
For output of signal that Comply with CD-ROM
Synchronizing signal of sub-code block.
33
ao tput of signal to DAC, Signal of Latch & L/R select, Signal
Sampling Hold
36
ain
2
Ww
SFSY
SBCK
bib w lw tw
WIN o
4 For correction monitor of C1, C2, single, double.
4 SFSY is Synchronizing signal of sub-code & frame. Clock of
eighth send to SBCK then read out the sub-code of P, Q, R, 5,
T, U,V, & W.
Output of Synchronizing signal (7.35KHz)
Data sub-code Q pass the CRC check then WRQ do “H”. It
detect at external, Data read out from SQOUT by send the
CQCk. RWC set the “H” by Micro Processor then it let
command by send with Synchronizing CQCK command data.
5
[se [vom [0 [vow oupurceaaqamniy
so [ am [0 [am ourpuriazazenra)
[so [con [0 | ths output can contol at Serial Control trom Micro Processor_|
[er [rests [1 [For test. Normal wime is non connection |
Pe ee Chip select Terminal. This terminal “L” : LC7866 is active
(Internal Resistor : Pull Down)
163 | xin | i _| Connection Terminal of crystal oscillation (16.9344MHz)
5
6
47
4
8
wn
Oo
Wn wn
BWN =
55
7
XOUT oO Connection Terminal of crystal oscillation (16.9344MHz)
RAM ADDRESS
GENERATOR
DAC OUTPUT
INTERFACE