Sanyo DC-PT80 - Page 27

- 27 -- 26 -
IC BLOCK DIAGRAM & DESCRIPTION
IC871 PCM1755D(Audio Digital-to Analog Converter)
IC BLOCK DIAGRAM & DESCRIPTION
IC818 SST39VF800A(Flash Memory)
Memory Address
Address Buffer
& Latches
Control Logic
X-Decoder
SuperFlash
Memory
Y-Decoder
I/O Buffer and Data
Latches
DQ
15 -DQ 0
CE#
OE#
WE#
Symbol
Pin Name
Function
To provide memory addresses. During Sector-Erase A MS -A 11 address
lines will select the sector. During Block-Erase A
MS -A 15 address lines will
select the block.
To output data during Read Cycles and receive input data during Write
Cycles.
Data is internally latched during a Write Cycle.
The outputs are in tri-state when OE# or CE# is high.
To activate the device when CE# is low.
To gate the data output buffers.
To control the Write operations.
To provide power supply voltage:
Unconnected pins
3.0-3.6V for SST39LF200A/400A/800A
2.7-3.6V for SST39LF200A/400A/800A
Address Inputs
Data Input/output
Chip Enable
Output Enable
Write Enable
Power Supply
Ground
No connection
AMS
1 -A 0
DQ 15 -DQ 0
CE#
OE#
WE#
V
DD
V SS
NC
1
INPUT
4
OUTPUT
1
3
GND
5
OUTPUT
2
Starting
circuit
Error
Amp.
Error
Amp.
Voltage reference
circuit
Overheat protect
circuit
Overheat protect
circuit
Drive
circuit
Drive
circuit
Overcurrent
limiting circuit
Rush current
provention circuit
Overcurrent
limiting circuit
Rush current
provent circuit
IC881 KRX101U(Switching)
VOUTL
7
V
COM
10
V
OUTR
8
BCK
1
LRCK
3
DATA
2
ML
15
MC
14
MD
13
SCK
16
12 11
DGND
4
VCC
6
AGND
9
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
I/O
I
I
I
-
-
-
O
O
-
-
O
O
I
I
I
I
TERMINAL
NAME
BCK
DATA
LRCK
DGND
NC
V
CC
VOUTL
V
OUTR
AGND
V
COM
ZEROR/ZEROA
ZEROA/NA
MD
MC
ML
SCK
Output Amp and
Low-Pass Filter
4x / 8x
Oversampling
Digital Filter
with
Function
Controller
Audio
Serial
Port
Serial
Control
Port
System Clock
Manager
System Clock
Zero Detect Power Supply
Enhanced
Multi-level
Delta-Sigma
Modulator
DAC
Output Amp and
Low-Pass Filter
DAC
DESCRIPTION
Audio data bit clock input
Audio Data Bigital Input
L-Channel and R-channel Audio data latch enable input
Digital ground
Analog power supply, +5V
Analog output for L-channel
Analpg output for R-channel
Analog ground
Common voltage decoupling
Zero flag output for R-channel / Zero flag output for L / R-channel (See Note 2)
Zero flag output for L-channel / No assign (See Note 2)
Mode control data input (See Note 1)
Mode control clock input (See Note 1)
Mode control latch input (See Note 1)
System clock input
Note: 1. Schmitt trigger input with internal pull-down.
2. Open Drain Output.
ZEROR/ZEROA
ZEROL/NA
: Open Drain Output for PCM1755
Q1
Q2
1
5
2 3
4
IC851 µPC37M31T(Regulator)