5-4
becomes an attenuator with a loss of approximately 10 dB. The output of the
preamplifier is then applied to double-balanced mixer MIX1. The use of a hot
carrier diode mixer assures minimal cross modulation and intermodulation
distortion in the receiver front end.
5.2.3
THE 45 MHz IF
The output from mixer MIX1 contains the desired signal upconverted to 45 MHz.
This signal is amplified by a low noise, high dynamic range MMIC amplifier that
establishes a good low noise 50-ohm termination for the mixer. Output of the first
IF amplifier is filtered by FIL1, a four-pole monolithic crystal filter of approximately
8 kHz bandwidth. This is the "topping" filter, which serves to remove the unwanted
secondary image, RF, and LO leakage as well as other unwanted upconverted HF
signals that fall outside the filter bandwidth. Following the topping filter is a second
MMIC amplifier stage and a second 2-pole filter. The total gain between the
receiver input and the 45 MHz output is approximately 12 dB. The maximum
allowable input signal with preamplifier on is approximately -3 dBm. Switching in
the attenuator raises this level to approximately +10 dBm.
5.2.4
THE SECOND MIXER/POST AMPLIFIER
The second mixer converts the 45 MHz IF signal down to the second IF frequency
of approximately 40 kHz. This mixer is a +13 dBm type, necessary to handle the
somewhat higher signal levels present at this point. Following the mixer, the signal
is passed through a low noise operational amplifier with a stage gain of 10 to a
phase splitter circuit with stage gain of unity. The phase splitter output drives the
differentially configured A/D input.
5.2.5
THE A/D CONVERTER
In IF/DSP receivers, system performance is highly dependent upon the
characteristics of the A/D converter that moves the signal from the analog to the
digital realm. In the SEA 245, A/D Converter U34 is a 24-bit, 96 kHz stereo ADC
with a dynamic range of 110 dB and greater than 100 dB signal-to-noise ratio. The
inputs to the ADC are full differential and the chip includes a reference filter and a
digital decimation filter, which minimizes requirements for anti-aliasing filtering.
The 40 kHz second IF signal from the main receiver and the 14.583 kHz second IF
signal from the 2187.5 kHz monitor receiver are each connected to one of the stereo
inputs of the ADC. The resulting digitized signals are then passed on to the system
DSP that is located on the CPU Board (ASY-0245-04).
5.2.6
THE CODEC
The CODEC is part of the CPU Board Assembly (ASY-0245-04) and uses AC'97
REV 1.03 architecture in a 18-bit sigma/delta configuration. The CODEC contains
both an A/D and a D/A converter. The A/D converter is used to convert transmitter
baseband signals into a digital bit stream suitable for processing in the DSP.
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