SEA 245 - Digital Signal Processor Operation; Receiver Automatic Gain Control System; Receiver Audio Circuitry

5-5
The D/A converter works in both receive and transmit modes. While receiving,
digitally processed receiver signals from the DSP engine are converted back into the
analog realm for processing through the amplifier/loudspeaker system. When
transmitting, digitally processed (and generated) baseband signals from the DSP
engine become the analog input signals to I/Q modulator chip U6 on the Mainboard
Assembly.
5.2.7 THE DIGITAL SIGNAL PROCESSOR
The main DSP engine in the SEA 245 consists of U7 on the CPU Board Assembly.
This is a TMS320VC5402, a specialized type of microprocessor which includes
such features as a 40-bit ALU, data bus with Bus-Holder feature, extended
addressing mode for 1Mx16-bit maximum external program space and many other
specialized features intended to facilitate the specialized math functions necessary
for DSP.
In the SEA 245, the DSP circuitry and firmware perform most of the signal
processing functions necessary to convert a radio signal into an audio signal and
vice-versa. These functions include frequency conversion, filtering, demodulation
and gain control in the receive mode and baseband signal processing, filtering and
generation in the transmit mode.
Since the DSP engine is actually a highly specialized type of microprocessor many,
indeed most, of the characteristics of the receiver and transmitter functions are
controlled by firmware algorithms embedded in the CPU Board memory. It is thus
possible to use the same system digital hardware to generate (and demodulate) voice
signals, TELEX signals, Digital Selective Calling signals or essentially any signal
format up to the bandwidth limitations of the system analog hardware. Receiver
AGC characteristics, transmitter bandwidth shaping and ALC functions are all
determined in firmware.
5.2.8 THE RECEIVER AGC SYSTEM
There is only one variable gain element in the receiver AGC system, JFET
preamplifier Q2. The amplifier passes signals whether or not it is enabled but, when
disabled, there is approximately 10 dB of attenuation with respect to the enabled
state. The actual AGC parameters are determined by the DSP algorithm and are
tailored to suit the mode selected. When receiving SSB signals, the AGC has the
usual fast attack-slow release characteristics suitable for SSB. The DSP software
monitors signal level and disables the preamplifier when necessary to protect the
A/D input from overload.
5.2.9 THE RECEIVER AUDIO CIRCUITY
The received signal is processed through the DSP engine and converted to an audio
baseband signal in the system CODEC. This signal then exits the CPU Board as the
SPKR.AF signal on pin 19 of J3 on the Mainboard and then passes through audio
gate U30C to the audio SEABUSS driver stage consisting of U31B and U31C.