Sega CD II - Page 20

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IC112 64k(8k x S)blt Static RAM
IC MB8464A-10LL
•Top View & Pin Layout
Vee
A12
WE
CS
2
As
A5
Ag
Ao-A12
:Address inputs
A4
A11
1/0
1
-1/0
8
:
Data inputs/outputs
As
~
CS
1
:
Chip select 1
A2
1 A10
CS
2
:
Chip select 2
CS
1
OE
: Output enable
WE
:Write enable
Vee
:Power supply (+SV)
GND : Ground
NC :Not connected
IC113 16/32-Blt Microprocessor
24
IC MC68HCOOOFN12 IC HDSBHCOOOCP-12
•Top View & Pin Layout
V, -
CLK
GND
GND
013
014
015
GNO
GND
A23
A22
A21
A19
All
A17
A16
A15
A1'
A13
• Block Diagram
A12
>
)
0
::D
0
0
::D
)
~
m
(/)
0
(/)
m
=
0
c:
0
,,
0
,,
m
m
::D
A5
::D
cs
A•
~
DDRES
BUFFER
Ao
cs
OE
INPUT
BUFFER
WE
cs
CS
1
~
CSz CS
IC TMPSBHCOOOT-12
• Signal Description
PROCESSOR
STATUS
M8800
PERIPHERAL
CONTROL
SYSTEM
CONTROL
VCC{2)
GND{2)
CLK
{~
FCO
FC1
FC2
E
{
iiMA
VPA
{='
- HALT
MC88HCOOO
--OVc c
--0 GND
( MEMORY CELL ARRAY
) 2sex32xe
---
1/0 GATE. COLUMN
DECODER
-
INPUT/OUTPUT CS
BUFFER
ADDRESS B
us
23-A1
}A
DATA BUS
}DI
,,
AS
RN/
-.
UDS
)
~
~
~
OT ACK
-
- BR
-
liG
-
BGACK
-
nsro
}
iPi:1"
iPil
5-00
ASYNCHRONOUS
BUS CONTROL
BUS
ARBITRATION
CONTROL
INTERRUPT
CONTROL
· '!'" ·