Sega CD II - Block Diagram

• Block Diagram (IC110)
CPU l/Fl==========================~A~DORE;:::~ss:;:==========================~
DATA BUS
RAMA°'
RAMA/3
RAMAl2
RAMA11
RAMAIO
RAMA9
RAMA8
R&MA7
RAMA6
RA~
RAMA4
RAMA3
RAMA2
RAMAi
AAMAO
RAMAX
1----....i INTERNAL
MEMORY
ADDRESS
POINTER
OCA
WAVE DATA
RAMCIB
RAMC28
RAMA .. .,,,.0
RAMA07
RAMAD6
RAMAO~
RAMA04
RAMAD3
RAMA02
llAMAOI
llAMAOO
RAMWEB
RAM OE
RAMCIB
RAMC21!
1-----.....ir-~T~IM:l:N:G~CON:::::TROL=:-~-------l..J-----..J---~:..._--~---~OAU
---~ SERIAL DAC 1/F HCUU
TESTI~
TEST2~
TEST3o--+
XIN XOUT RE ETR
IC111 1 Mblt CMOS Masked Programable ROM
IC SEGA-C02 BOOT ROM EP IC SEGA-C02 USA BOOT ROM
IC MEGA-C02 (PAL) BOOT ROM
•Top View & Pin Layout
01 1
Oo 1
Vee
CEz!CE
1
/D.C
OE
2
/0E
1
/D.C
A15
A14
A13
A12
Au
A10
1 Ag
GNO
As
A1
As
A5
A4
A3
Az
OE
1
/0E
1
-,, ___ _r-
• Block Diagram
A.
A.
A,
A,
A.
A,
A.
A,
~
A~
A ..
A.
A.,
Au
A.,
A.
• Operation Mode
· et.
CE, OE,
I
x
x
x
I
x
A A
I
A
A
x
A
A A
1-----oOllCLJ(
L--------t"-----t.OLRCLK
-----tlODA'7R
i.....----t., _______ _r-----.ODA7L.
LATCH
IC MEGA-C02 BOOT EP MULTI
OE
1
OE
2
MEMORY CELL MATRIX
a:
85538 x 18
w
CE
1
""
BIT
""
:::>
ID
I-
~
CE
2
3:
OE, Mode
Output
x
Non-
x
selective
x
High Impedance
I
Selective
A
Data
23