Sega GENESIS II User Manual

Pin
I
Name
1
110
1
Function
No.
I
Input/output request signal.
"0" is output when the address for input/output is on the low-order 8 bits (AO-A 7) of the
16 IORQ 0
address bus when an input or output is given. The IORQ signal is also output together with
I
the Ml signal when an interrupt is acknowledged to infonn the peripheral LSI that the
I
interrupt response vector can be superimposed on the data bus.
i
READ signal.
18
RD 0
"0" is output while the MPU can accept the data from a peripheral LSI. The data in the
designated LSI or memory is gated by this signal and can be superimposed on the MPU
data bus.
I
WRITE signal.
19
WR
0
This is output when the data to be stored in the memory or peripheral LSI is superimposed
on the MPU data bus.
Bus acknowledge signal.
When the BUSREQ signal is input, the BUSACK signal infonns the peripheral LSis that
20 BUSACK
0
the address bus and data bus of the MPU and the MREQ, IORQ, RD and WR signals have
been set to high impedance.
WAIT signal.
21
WAIT
I
The
WAIT signal infonns the MPU that the designated memory or peripheral LSI is not
ready for data transfer. The MPU continues in the wait state as long as the WAIT signal is
''0".
Bus request signal.
22 BUSREQ
The BUSREQ signal requests to set the address bus and data bus of the MPU and the
I
MREQ, IORQ, RD and WR signals to high impedance. BUSREQ is usually used as the
wired OR and a pull-up resistor is connected externally.
Reset signal.
23
RESET
I The RESET signal initializes the MPU and should be
active ("0") for at least 3
clock-signal periods.
Signal that indicates machine cycle I.
-
"0" is output together with the MREQ in the command operation code fetch cycle. When
24
Ml
0
2-byte operation codes are executed, M I is output each time the operation code is fetched.
M I
is output with the IORQ signal in the maskable interrupt acknowledge cycle.
Refresh signal.
25 RFSH
0
"0" is output when the address that refreshes the dynamic memory is on the low-order 7
bits of
the address bus. The MREQ signal also goes active ("0") in this state.
26 Vss
-
OV power supply
27-32
16-bit address bus.
34-38
AO-AIS
0
Address the memory and input/output ports.
40-44
The address for refreshing is output during refreshing.
19

Sega GENESIS II Specifications

General

Brand	Sega
Model	GENESIS II
Category	Game Console
Language	English