Sharp LC-24LE210E - Block Diagram

35
LC-24LE210
LC-24LE220
2.3. IC 1001 (MSD3303GX)
2.3.1. Key Features
• Master CPU with MMU.
• DRAM controller supporting up to two 16-bit DDR2 interface.
• Power control module with ultra low power MCU available in stand by mode.
• Parallel interface for external parallel NOR fl ash and NAND fl ash support.
• H.264 decoder. Support resolution up to HDTV ( 1080i, 720p) .
• MPEG-2 decoder.
• Video analog processor.
• NTSC/PAL/SECAM Video Decoder.
• Support Teletext mode.
• Two CVBS video outputs.
• Eight confi gurable CVBS, Y/C, S-video inputs.
• Multistandard sound Processor.
• AC3 decoder.
• I²S digital audio output.
• Six L/R audio line-inputs.
• SIF audio output.
• Stereo L/R output for main speaker.
• Two HDMI / HDCP compliant input port.
• CEC support.
• Fully programmable scaler and display processing.
• Support up to 10 bit LVDS full HDTV panel interface.
• Support USB 2.0
• Support Common Interface for conditional access.
2.3.2. Block Diagram
2. Detailed ICs Information, DUNTKF639WE (Main Unit) (continued)
TRANSPORT
DEMUX
MPEG2/
MPEG4
NTSC/PAL/
SECAM
DECODER
SIF
DEMOD
AUDIO
DSP
ANALOG
FRONT-END
INPUT
PROCESSING
DEINTERLACE
and SCALING
VIDEO
OUTPUT
CONTROLLER
AUDIO
OUTPUT
CONTROLLER
DDR2-16x2
DRAM I/F
Processor *2
USB 2.0
HOST *2
/
YPBPR x3
-VIDEO x8
I
N (1P, 1S)
I2S INx1
PDIF IN x1
DDR-2 DRAM
I2CS, JTAG I/F
UART: x3
I2CM: x1
SPI: x1 (2 cs)
PWM: x4
PFLH: x1
DVB-CI: x1
PHY I/F
Dual LVDS
L/R OUT x3
S/PDIF OUT
VIDEO
PROCESSING
GRAPHICS
ENGINE
SIF IN x1
B
S OUT x2
I2S OUT
TV Encoder
DAC
Power
Management
IR, CEC, INT,
HSYNC, SARx4
HW JPD
ADC
L/R x6 ADC
AUDIO
DSP
VIDEO
PROCES
SING
H.264/
RM
MII or RMII
10/100M
EMAC