LC-32X20E/S/RU, LC-37X20E/S/RU
5 – 15
2.9. IC3301 (RH-iXC010WJQZQ)
2.9.1 Pin Connections and short description
Pin No. Pin Name I/O Pin Function
Ball Assignments for CPU Host Interface.
K20, K19, K18, K17, L20,
L19, L18, L17
A_D[7:0] I/O Multiplexed address and data bus powered by VDDH/VSS.
M17, M18, M119, M20,
N20, N19, N18, N17
ADDR[7:0] I CPU Address. (Not connected)
J18 ALE I Address latch enables.
J19 WR# I CPU Write.
J20 RD# I CPU Read.
H17 SDA I/O I2C data.
H18 SCL I I2C clock.
J17 CPU_CS I UX chip select pin from MCU. Active Low.
Ball Assignments for Analog Support Interface.
W1 XTALI I Input for Clock Synthesizer. Supports 24MHz Oscillator or crystal powered by ana-
log PLL.
Y1 XTALO O Used in conjunction with XTALI for 24MHz crystal output powered by analog PLL.
U2 MLF1 I Low pass filter node for memory clock PLL powered by analog PLL.
R4 PLF2 I Low pass filter node for video clock PLL powered by analog PLL.
Ball Assignments for Analog Input Interface.
Y4 CVBS1 I Composite video input 1.
V6 Y_G1 I Y input 1 of component or G input 1 of PC RGB.
W6 Y_G2 I Y input 2 of component or G input 2 of PC RGB.
Y6 Y_G3 I Y input 3 of component or G input 3 of PC RGB.
W2 CVBS_OUT1 I CVBS Output 1. (Not connected)
V2 CVBS_OUT2 I CVBS Output 2. (Not connected)
V9 C I C input of S-Video.
W9 PB_B1 I PB input 1 of component.
Y9 PB_B2 I PB input 2 of component.
Y10 PB_B3 I PB input 3 of component.
Y8 PR_R1 I PR input 1 of component.
W8 PR_R2 I PR input 2 of component.
V8 PR_R3 I PR input 3 of component.
W4, V4 FS2, FS1 I SCART function select 2, 1.
U4, Y5 FB2, FB1 I SCART FB input for Port 2, Port 1.
V10 AIN_H I Hsync input (PC RGB input)
U10 AIN_V I Vsync input (PC RGB input)
U8 PC_R I PC Red input.
Y7 PC_G I PC Green input.
W10 PC_B I PC Blue INPUT.
Ball Assignments for Capture Interface (TV & RGB).
U18, U19, U20, T20, T18,
T17, R19, R20
DPB[15:8] (DP_B[15:8]) I/O Digital input port [15:8] (Output reserved)
Y12, U13, V13, W13,
Y13, Y14, W14, V14,
U14, U15, V15, W15,
Y16, W16, V16, U16,
U17, V17, W17, Y17,
Y18, W18, V18, W19
DPA[23:0] (DP_A[23:0]) I/O Digital input/output port [23:0]
T19 DPB_CLK (CLK_B) I/O Digital port B CLK input/output. (Not connected)
Y15 DPA_CLK (CLK_A) I/O Digital port A CLK input/output.
W20 DPE_DE (DE_B) I/O DE input/output of Digital port B.
Y20 DPA_VS (VS_A) I/O Vsync input/output of Digital port A.
Y19 DPA_HS (HS_A) I/O Hsync input/output of Digital port A.
V20 DPB_VS (VS_B) I/O Vsync input/output of Digital port B. (Not connected)
V19 DPB_HS (HS_B) I/O Hsync input/output of Digital port B. (Not connected)
P19 HS I/O Hsync output for Digital port.
P17 VS I/O Vsync output for Digital port.
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