Sharp MZ-800 - 1.3 Appearance

MZ-800
Pin
Signal name
1/0
Functional description
Note
No.
1 CPU 0
CPU clock (3.547 MHz)
2
5V
-
Power supply
3
GND -
Ground
4 ADO
I
I
I
CPU address bus
19
ADF
20
DTO
I
I
1/0 CPU data bus
27
on
28 GND -
Ground
-----0---
VCC
Power supply
29
-
--30
MREO
I CPU MREQ signal
Negative logic
--
31
RD I CPU RD signal
Negative logic
32
WR I CPU WR signal
Negative logic
33
RFSH I CPU RFSH signal
Negative logic
34
IORQ I CPU lORQ signal
Negative logic
e----,.;-----
I---
I CPU Ml signal
Negative logic 35
Ml
---36- --
SEL1 0
System RAM address multiplexer select signal
37
CASB 0
System RAM column address strobe signal
~8
INH5 0
Inhibit bank (OUT $E5) select signal (uH" = Inhibit).
OPEN
f------
0
Vertical blanking signal
Negative logic 39
VBLN
1-- 40
GND
-
41 VRAS 0
VRAM RAS control signal
Negative logic
42 IJCli:S 0
VRAM CAS control signal
Negative logic
-
43 VADO
I
I
0
VRAM address signal (multiplexer output)
50
VAD7
_._--
51
VOE 0
VRAM output enable
Negative logic
52
VCC
-
Power supply
53 GND
-
Ground
54
VRWR
0
VRAM write signal
Negative logic
55
VAO
I
I
1/0
VRAM data bus (standard RAM)
62 VA7
--- 63--f--
VCO
I I
1/0 VRAM data bus (option RAM)
70 VC7
I----
i
,--
I-----
SBCR
0
Color sub-carrier wave
--ii--
I---- RED
0
Video signal, red
--73--
BLUE 0
Video signal, blue
-~---
----GREN
0
Video signal, green
1-----
YITN 0
Brightness control signal
75
1-------
VSYN
0
Vertical sync signal
Negative logic
76
77
HSYN
0
Horizontal sync signal
Negative logic
f---
--
GND
78
-
------
-. ---
79 VCC
-
80
CLKO I
Clock input (17.7344 MHz)
-_ .. _---
81 CROM
0
ROM chip enable
Negative logic
-8-2-
KEY
0
8255 chip enable
Negative logic
---a3-
f------NTpL
I NTSC/PAL selection (PAL - "L")
GND
-- --------f----
I Test pin ("H" - test mode)
GND
~~=p~SD~
I
MZ-700/800 mode selection ("L" = MZ-700 mode)
86 lOWR 0 Sum of CS and WR of 1/0 controlled by the custom IC
Negative logic
C---
S7
--
lORD
0 Sum of CS and RD of 1/0 controlled by the custom IC
Negative logic
-------aa--
--------cR S
0 1/0 $BO - $B4 chip enable
OPEN
89
SIO
0
1/0 $F4 $F7 chip enable
OPEN
90
RSTO
0
Reset output
Negative logic
f--
-----
I
Manual reset input
Negative logic
91 MNRT
92 PORT
---
I
Power on reset input
Negative logic
93 WTGD 0 Wait signal to CPU
Open drain
94
JOY
0 Joystick chip enable
Negative logic
95
CPR
0
PlO chip select
Negative logic
96
PSG
0 76489 chip select
Negative logic
97 CKMS
0
8253 musical interval clock
1------g8
53G
0 8253 musical interval ONIOFF gate signal
---
99
C53
0 8253 chip enable
Negative logic
100 TEMP
I MZ-700 mode, $E800 tempo input
* Term "OPEN" represents the signal not used on the board.
10