Sharp MZ-800 - CRTC Register Map

(Ex.)
An example of the pallet in use in the 320 x 200,
16-color mode
• Assume that the pallet register has been set to the
following.
l
PL TO = Black
PLT1 = Cyan
PLT2 = Red
PL T3 = Magenta
• When SWo is set to "0" and SW, to "0", the pallet is
applied
to four colors in group 1 (ill = 0, N = 0) and
it results in
the color as shown in CD of the table right
(yellow to cyan).
• When SWo is set to "0" and SW, to "1", four colors
of group 3 (ill = 0, N = 1) becomes the display color
set by the pallet.
• Therefore, any color can be chosen out of 16 colors
against
four colors of color group selected by SW1
and SW2.
• For group other than selected by SWo and SW" the
color that I - N outputted on B, R, G, I is displayed.
c.
Plane data
'"
e
Cl
I II ill N
0 0 0
0
~
c.
1 0 0
0
'"
e
0
1 0 0
Cl
1 1 0 0
0 0
1 0
N
1 0
1 0
c.
'"
0
0
1
1
0
l5
1
1 1
0
0 0 0
1
M
1 0 0
1
a.
'"
e
0 1
0
1
Cl
1 1 0 1
0 0
1 1
..
1 0 1
1
c.
'"
0
0 1
1 1
l5
1 1
1 1
Border color
MZ-800
Display color of SWo = 0
SWo = 0
1- N ..... RGBI SW, = 0
SW,
= 1
Black
PLTO = Bleck Black
Blue
PLT1 =Cyen
Red
PLT2 = Red
Magenta
PL T3 = Magenta
Green
+-
+-
Cyan
+- +-
Yellow +-
+-
White
+- +-
Gray
+- PLTO = Gray
Light
blue
+-
PLT1 = ~\~~t
Light red +-
PLT2 = ~~ht
Light magenta
+-
PLT3 - light
- magenta
Light green
+- +-
Light cyan
+- +-
Light yellow +-
....
Light white +-
+-
• As the CRTC has a 4-bit border color register, it
permit to use any border color out of 16 colors.
4-2-9. CRTC register map
• VRAM control
• Data display on the video screen
Control I/O address map
1/0 address
--
H
l
IN/OUT
(B)
(C,
*)
---
CC
0
---
CD 0
---
CE 0
---
CE
I
-- --------- --~-
01 CF 0
02
CF
0
03
CF 0
04
CF
0
05
CF
0
06
CF 0
07 CF 0
~
FD 0
•
Border register (OUT 06CF
H
)
MSB LSB
BCOLI~ __ X __ ~ __ X~~ __ X __ ~ __ X~~ __ -L __ G __ ~ __ R~I~_B~
• B, R, G, and I becomes "0" (black) when reset.
Write format register (WF)
Read
format register (RF)
Display mode register (DMD)
Status read
Scroll offset register l (SOF1), 8 bits
Scroll offset register R (SOF2), 2 bits
Scroll width register (SW), 7 bits
Scroll start address register (SSA), 7 bits
Scroll end address register (SEA), 7 bits
Border
color register (BCOl), 4 bits
Superimpose bit (07) (CKSW), 1 bit
Pallet register
26
Written by indirect
OUT command.
B register
<- 0-7
QUT(C),A