Sharp OZ-9600II User Manual

OZ-9600 IT
IQ-9200
2. Description of LSI
2-1. CPU (LH58061M)
1) Introduction
@ CMOS process
@® 8-bit CPU (operand at 8 bits)
@ Firmware ROM (decoder)
@ 240 bytes RAM
® WO port
(Input) Key input
System control input
CMT input
UART input
General purpose input port
Key output
Address output
Chi enable output
LCD driver control output
Memory control output
(Output)
2) Block diagram
wadoosa
yaauo-
Sub-clock output
CMT output
UART output
General purpose output port
Data input/output
Power supply line
Oscillator line
(input/output)
(Others) ;
© Internal circuit
Oscillator circuitMain, subsidiary (for timer)x2
Reset circuit :
UART ,
@ Supply voltage3.8V~6.0V
Operating temperature range-5~55°C
@® Not the bit slice microprocessor.
No arithmetic function for data above 8 bits.
@ No multiply instruction capability.
@ Does not contain ROM type internal memory ROM.
® 100-pin TQFP (flat plastic package)
@ No radiation protective design provided. °
TXD
-
@D
X4
X3
CEO
-----------
a
a
CE CONTROL
‘| DIVIDER suBosc |:
INTERRUPT
CONTROL
YSdIAId
LI
RESET TEST ON LHCTRL Cl CO
(240Byte)
43aqoo3a
yaauo-d
ees
py -ORDER
DECODER
REGISTER
CONTROL REGISTER
\S Fee
p-ORDER
DECODER
m
MRQ WR
REGISTER |
CONTROL
JOYLNOO ASIGOW SSSYUGdV
LJ
voD
DIOO ---- DIO7 GND
Fig.2 LH5806AM block diagram
TOULNOO UNVE
uasung ssaucay
Y3445N@ LHOd-3
x x x
a
POWMOAAH
«x «OK
PES
CJA20

Sharp OZ-9600II Specifications

General

Brand	Sharp
Model	OZ-9600II
Category	Organizer
Language	English