10
All and more about Sharp PC-1500 at http:/lwww.PC-1500.info
CD
4JOS
Through
this
lin
e can be supp
li
ed the clock to
an
external system since the clock in the
same
pha
se
as
the
CPU
internal basic clock is on this lin
e.
Co
nnection of the 2.6M Hz
crystal oscillator
to
XLO
and
XLI
wi
ll s
upp
ly the
cl
ock
of
I.3M Hz.
© RIW
M
emory
write signa
l.
A low on this
li
ne causes the
CPU
to send
data
on
the
da
ta bus.
0
00
Outpu
t disable signa
l.
/\
high on this line causes the C PU
to
prohibit
data
out
put to the
externa
l
de
vice.
It
is used in w
ri
t
in
g
data
to the m
emo
ry.
<l>OS
M
EO
or
M
£1
1
R/W I
OD~
~
A
~-
-
-~
--'
/
00
~0
7
_..
----
--<
(
MEMORY
DATA
:
)
---
--
~<
\_
__
cP
_u_o_AT_A_
.,_.;)---
--
- -
Memory read cycle
Memory wrrto cy
cle
© RESET
CPU
reset input. Hi
gh
state
of
this sig
na
l resets the
CPU
and
the c
on
tents
of
the
addr
ess
FFFEH
is set to the register PH
and
the contents
of
the
add
ress
FFFFH
to the
register PL.
Wh
en it
turn
s
fr
om
high to low leve
l.
it star
ts
pro
gra
m executi
on
from the
ad
d ress
of
the
pro
g
ram
counter.
@ NMI
Non
-maskablc interrupt input. High state
of
this signal causes i
ntermp
t to the
CP
U, to
whi.ch the
CPU
unconditionally responds
and
starts the interrupt
proc
essing routine
of
whi.ch h
ig
h ord
er
byte address is r
ep
resented by the
add
ress
FFFCH
and
low order
byte
add
ress by
FFFD
H.
Do
not
sell this PDF !!!
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