Sharp PC-1500 - Page 17

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@ Ml
Mask ab le interr upt input. When the inter rupt enable fl ag IE is act i ve . a high on the pin
Ml requests in terrup t, to which the CPU starts to execute the interr up t pr ocessing
rou tine whose hi gh or de r byte add ress is represented by the address FFF8 H and l ow
order byte add ress by FFF9H .
How instruction execution address is determined against the reset and interrupt
input
Addr ess
EOO OH
El 71 H
E22B H
E22CH
fffBH
9
A
B
c
D
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FFFFH
External memory
....--
~
-
-
~
-
::.----..:: -
1--1
-
El H
I
71H
r
E2H
f
2CH
E2H
f
28H
EOH
l
OOH
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-
-..
Staft addn . ~ss
by RESET inp ut
Start add ress
by Ml input
Start address
by NMI i npu t
Start add re ss
by ti me r interrupt
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