Sharp PC-1500 - PC-1500 Servicing and Maintenance; PC-1500 Irregular Condition Handling and Reset; PC-1500 Flexible Printed Cable (FPC) Replacement

All and more about Sharp PC-1500 at http:/lwww.PC-1500.info
@ WAIT
CPU wait signa l. A high on this line \top~ the clock <P so 1ha1 th e CPU halts its
operation. /\s soon as WAIT rnrns lo\\. the CP U resumes the operation .
Basic clock
Cloc k
WAIT
np1 1op
WA
<POS
NOTE : WA is l he flipfl op dedica t ed 10 WA IT , by wh ic h the WA IT i np ut is received at the falhng
edge of the cl ock <!>O S Because the CPU operating clock <P stops whe n W/\ 1s h ig h, ii
makes the CPU .stopp ed, conseque ntly.
@ HO ..., H7
I. C D bac kp late si gna l ou 1pu1. /\s the liquid cr ys ta l displ ay (LCD) is dr iven by
backp l ate signals and segme111 ~igna l s. the CPU co ntr ols the ba c kp late signals.
@ VA, VB, VM, VDIS
I.CD backplate pow er sup pl) input>.
® HIN
Input signal to th e cou nt er from which the L CD backplate signab 11 0- 11 7 arc
genera ted . orrnally. connec ted to pin ll A of the CPU.
@ HA
CPU in 1e r m1 I divider output pin. It is u se d for· the basic clock that dr ives the LCD that
co nn cc1c cl w it h H IN a nd the segment signal gen erating LS I.
@ DISP
I. CD on/ off control signal ntllpul which can be set or reset by m ea ns of instru ct ion.
@ BFO, BFI
RF nipflop output ( BFO ) and input ( IJ FI). The BF nipllop is n:..,.ct by th e OFF
instruction from the CPU. and ''ill be~• when the input BF! is turned to high level.
BFO is in low level wh en the BF flipflop is set and in high level when rc~ct.
As VGG is power s uppl y to the BF ni pO op. 1 he contents of the nipOop arc retained a~
l ong as VGG is in supply .
'ormally. it is u sed fo r mem ory backup system.
Do not sell this PDF ! !!
13