18
All and more about Sharp PC
-1
500 at http:/lwww.PC-1500.info
Non-maskable interrupt processing sequence
P1 1-
•P
lnsttuction
fe1ch
If S=100
5H
before
go
i
ng
i
nto
the interrlJpt
pr
oc
ess. ti
1e
contents of T and P are
stacked. and
it
becomes S=1002H after the
pro
cessing.
N
T-
(S)
Value
of
S
'1002H
s -
1-s
after u
1t
orrup1
0-1£
1
003H
PH
0-·
IR
O
1
004H
Pl
PL
- (S)
Va
l
ue
of
S
-i>
1
005
H
T
S-
1-S
bef
o
re
in1errvp1
PH
·S
s -
1-s
(
FF
FCH
)
-PH
(
FF
FOH
)- ·
PL
0 Maskable interrupt
When
MI
is tu med
fr
om low to high leve
l.
it
sets t
he
ll
ipflop I R2 acti
ve
. If the
int
errupt
ena
bl
e IE is acti
ve
at this point. i
nt
errupt is requested to the CP
U.
so that
th
e
CPU
sta
rt
s executing the interrupt proce
ssi
ng
af
ter comple
ti
on of current
inst ruction execu
ti
on. I R2
wi
ll
be
reset
in
a course
of
t
he
im
errupt
prO~
'l':
s~
.
Wh
en interrupt request is issued
wh
il
e IE is inactive. t
he
in
t
er
ru
pt
wi
ll be ignored
even though I R2
is
se
t.
MI
in
pu
t is sam
pl
ed
in
the same manner as in the case of NM I
Maskalble interrupt processing sequence
T-
<S
)
s-
1-
s
0-1(
0-
I
R'l
Pl - (S
S
l
~
·
S
PH
·,S)
S I •S
fff8H}
•PH
F
ff'9H
)-P
L
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not
sell this PDF !!!
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