All and more about Sharp PC-1500
at
http:
/lwww
.PC-1500.info
<D
Timer
in
terrupt
When
i111errup1
i,
1cquC>tcd
from the timer.
i1
sets
1he
flipflop l R l active. If
1he
intcrrupl enable l E
i,
acti\e
at
thi~
point. the CPU >1arb executing the interrup1
procc sing
al"ier
completion
of
curren
t
in~truction
execu1ion. and l R l
"ill
be
reset in
a
course
of
1h
c interrupt process.
When imcrrupl
i>
re<1ue
s
1ed
while I
F.
is
inactive.
1hc
i111
crrupt
will
be
ignored even
I ho ugh
lR
I
i'
SC
I.
Timer interrupt
proc
es
.s
ing
se
quence
~~~~~~~~~~~~~~~~
--~
~~~~
~
•u
-•
Return
to
ma
in
routine
T • S
S l
_...,S
0
·I
(
0
·1
~1
PL
•\S
s 1-s
l
)H
• S
s 1-s
rFrA.H.-.P-i
r
rr
SH
.
-Pl
The RTI instruction
is
u'ed
for returning from
1he
i111errup1
procc>>ing rou1inc
to
1he
main
routine.
Because the
co
n1<:11b
of
th
e T register and 1he program coun1cr arc s
1or
cd in
1he
stack a11he
beginning
of
the interrup1 processing routine.
th
e conte
nt
s of the T register in the stack
re
turns by the RTI instruction. Since the int
er
rupt enllblc llag IE
is
co
ntained in
1hc
T
regis1cr. the
cnnlcnb
of
IF immediately before lhc
in1
cr
rup1
returns by
th
e RTl
instruction.
To
disable
ma
skablc
or
timer
i11t
er
rup1
by
1hc
main routine af t
er
rc1t1mi11g
from the
interrupt processing routine.
1he
bit in the s1ack corresponding
10
the
fla
g IE must be reset.
Priority order
of
interrupts
(I)
:>lon
-
ma
skablc imerrupt responds
to the interrupt
rcqu
c't
"ha1e,cr
1 he CPU internal stare may be.
Al
so
. it
r
c~pn
n
d
s
in the
ti
rst
prio
rity
e\
·en
during
CXCCLl
l ion
Of
int
errupt
ro
uti
ne by other interrupt.
Do not sell this PDF ! !!
19
To Next Page
Loading...
